3D Stacked Single Crystal Memory via Ion Implantation Splitting
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving high storage density and low costs per bit due to the use of polycrystalline silicon, which results in unacceptably high off-current and poor device performance due to grain boundaries and intragranular defects, while processes for single crystal silicon devices are complex.
Innovation Solution
A method for manufacturing a three-dimensional stacked memory structure using multiple layers of single crystal semiconductor material separated by insulating material, achieved through ion implantation to create defect layers for layer splitting and bonding, enabling the formation of high-performance memory cells with improved transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polycrystalline silicon is used for memory cells, then manufacturing complexity is reduced, but off-current increases and device performance deteriorates
Solution Approach 1:
The single crystal silicon body is segmented into multiple thin layers through controlled splitting. This segmentation creates multiple bonding interfaces that can be stacked to form three-dimensional memory structures, maintaining single crystal quality while enabling complex 3D architectures. The splitting process creates defect layers that facilitate controlled separation into discrete layers.
Solution Approach 2:
The invention transitions from two-dimensional planar memory structures to three-dimensional stacked structures by bonding multiple single crystal layers vertically. This dimensional transition increases storage density while maintaining the performance benefits of single crystal silicon, as each layer can be processed independently and then stacked to form the final 3D memory device.
2Reliability
If single crystal silicon is used for memory cells, then off-current is reduced and device performance is improved, but manufacturing complexity increases
Solution Approach 1:
Defect layers are introduced into the single crystal silicon body before the splitting process. These preliminary defect layers serve as predetermined separation planes that guide the splitting process, making it easier to obtain uniform thin layers with controlled thickness. This preliminary action simplifies the overall manufacturing process by providing built-in separation guides.
Solution Approach 2:
The defect layers act as intermediaries during the splitting process, facilitating controlled separation of the single crystal silicon body into thin layers. These defect layers enable the splitting process to proceed at lower temperatures and with greater precision, reducing the complexity of the manufacturing process while maintaining single crystal quality in the final layers.
3Quantity of substance
If multiple layers are stacked to increase storage density, then data per unit area increases, but process complexity increases
Solution Approach 1:
Multiple independently processed single crystal layers are merged through bonding to form a integrated three-dimensional memory structure. This merging process combines the advantages of single crystal silicon from each layer while creating a high-density stacked architecture. The bonding process unifies the separate layers into a single functional device with enhanced storage capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for the creation of high-density, low-cost 3D memory devices with improved performance by utilizing single crystal semiconductor layers, reducing off-current and enhancing device characteristics such as threshold voltage and transconductance.
Implementation Method 1
Ion implantation is performed on a first single crystal semiconductor body to form a defect layer within the first single crystal semiconductor body. The defect layer facilitates splitting of the first single crystal semiconductor body into a first layer of single crystal semiconductor material and a second layer of single crystal semiconductor material.
Data Source
AI summary
Technology is described herein for manufacturing a three-dimensional 3D stacked memory structure having multiple layers of single crystal silicon or other semiconductor. The multiple layers of single crystal semiconductor are suitable for implementing multiple levels of high performance memory cells.