Single-Die DC-DC Switching Array Layout for High Current
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Solution Overview
Problem
Conventional switch-mode voltage regulator circuits require multiple manufacturing steps and metal layers to handle high current and power, leading to increased costs and performance degradation at high frequencies, while also failing to meet miniaturization requirements due to complex signal routing and large silicon area consumption.
Innovation Solution
A layout method that forms an array of switching elements with reduced ON resistance and integrates gate driver circuits on the same semiconductor die using a single metal process, along with a semiconductor flip chip die and lead frame structure with inter-digital finger-shaped electrical leads, to minimize manufacturing steps and silicon area while maximizing current delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional layout uses three separate semiconductor dies for controller, high-side MOSFET, and low-side MOSFET, then high current and high power demands can be handled, but manufacturing complexity increases and silicon area consumption increases
Solution Approach 1:
The patent merges the controller, high-side MOSFET, and low-side MOSFET onto a single semiconductor die, eliminating the need for three separate dies and their associated bond wires. This integration reduces manufacturing complexity while maintaining the capability to handle high current and power demands through optimized layout and interconnection structures.
2Power
If conventional layout uses three separate semiconductor dies connected by bond wires, then high current handling is achieved, but interconnection resistance increases at high switching frequencies
Solution Approach 1:
By integrating all active components onto a single die, the patent eliminates bond wire interconnections entirely, removing the source of parasitic resistance and inductance that degrade performance at high switching frequencies above 500 kHz.
Solution Approach 2:
The patent transitions from a three-dimensional multi-die stacked architecture to a planar single-die layout, allowing direct on-die interconnections that reduce parasitic effects compared to vertical bond wire connections through multiple die interfaces.
3Power
If conventional layout uses three die attachments, then high power switch-mode voltage regulator functionality is achieved, but silicon area consumption increases
Solution Approach 1:
The patent consolidates three separate dies into a single integrated die, dramatically reducing the total silicon area required. The integrated layout optimizes the arrangement of switching elements and interconnections to minimize footprint while maintaining high power capability.
4Power
If conventional method uses two or more metal layers for signal routing, then high current and power delivery is achieved, but manufacturing steps increase
Solution Approach 1:
The patent integrates power delivery and signal routing functions into a unified layout on a single die, reducing the need for multiple metal layers and complex interlayer routing. This simplification reduces manufacturing steps while maintaining the capability to deliver high current and power.
Data Source
AI summary
A layout method that enables a high power switch mode voltage regulator integrated circuit to generate a large output current and achieve substantially low switching loss is disclosed. The layout method includes forming an array of switching elements on a semiconductor die, each switching element including a plurality of discrete transistors configured to have a substantially reduced ON resistance; and forming a plurality of gate driver circuits on the same die among the switching elements, all using a single metal process. Each gate driver circuit placed substantially close to and dedicated to drive only one switching element so that the gate coupling capacitance resistance product is substantially reduced.