Single Global Data Line Semiconductor Memory Device
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Solution Overview
Problem
Conventional semiconductor memory devices with hierarchical bit line structures face issues such as erroneous data reading, potential level imbalances, and increased leakage current, leading to operational errors due to the differential amplifier's sensitivity and load capacity imbalances.
Innovation Solution
A semiconductor memory device with a single global data line and dual output circuits that selectively control the potential levels of local bit lines to maintain the global data line at a stable high potential, preventing erroneous readings and reducing the likelihood of differential amplifier errors by balancing load capacities and managing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single global data line is used to reduce leakage current and circuit area, then the number of global data lines is reduced, but the potential level stability deteriorates due to discharge from multiple transistors
Solution Approach 1:
A precharge transistor is introduced as an intermediary component between the power supply and the global data line. This transistor selectively charges the global data line to a high potential level when needed, counteracting the discharge effect from multiple connected transistors and maintaining potential stability without requiring multiple global data lines.
Solution Approach 2:
The global data line is precharged to a high potential level before read operations occur. This preliminary charging action ensures that the line maintains its potential despite subsequent discharge from transistor leakage, enabling reliable operation with a single global data line.
2Quantity of substance
If an inverter is connected to one of the local bit lines to enable single global bit line reading, then the number of global bit lines is reduced, but the load capacity imbalance causes differential amplifier errors
Solution Approach 1:
The patent intentionally introduces asymmetry by connecting an inverter to one of the two local bit lines (BL0 or BL1). This asymmetric configuration enables the use of a single global bit line while the inverter's feedback mechanism compensates for the load imbalance, maintaining differential amplifier reliability.
3Measurement precision
If the potential difference between local bit lines is amplified by a differential amplifier, then data reading capability is enabled, but the higher potential bit line's potential is lowered toward Low level causing erroneous readings
Solution Approach 1:
The global data line is precharged to a high potential level before the differential amplification process. This preliminary action ensures that even if the differential amplifier lowers the potential of the higher potential bit line, the global data line maintains its high level long enough to complete accurate data reading.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the chances of the semiconductor memory device operating erroneously, maintains the global data line at a stable potential, and ensures proper data reset, thereby enhancing the reliability and sensitivity of the differential amplifier.
Implementation Method 1
a differential amplifier configured to amplify a potential difference between the first and second local bit lines
Data Source
AI summary
A memory bank of a semiconductor memory device includes: a plurality of memory cells; first and second local bit lines; a differential amplifier configured to amplify a potential difference between the first and second local bit lines; a connector to which a global data line is connected; a first output circuit configured to selectively output, according to a potential level of the first local bit line, a first potential to the connector; and a second output circuit configured to selectively prevent, according to a potential level of the second local bit line, a potential of the connector from being affected by an output of the first output circuit and being equal to the first potential.