Single-Instruction GPU Texel Access with Coordinate Offsets

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Solution Overview

Problem

Conventional graphics processing units (GPUs) face inefficiencies due to the need for multiple texel access operations, which can be resource-intensive when handling large numbers of texels for texture processing and postprocessing in 3D applications.

Innovation Solution

GPUs are configured to perform texel access operations on multiple texels responsive to executing a single instruction, determining coordinates and offsets to access multiple texels within a texture, and perform operations such as loading, storing, and merging texel data in general-purpose registers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple texel access operations are performed sequentially using conventional GPU instructions, then each texel can be accessed with precise control, but the processing time and resource consumption increase significantly

Engineering Contradiction:
Improvetexel processing throughputVSAvoidprocessing time for multiple texel operations
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent combines multiple texel access operations into a single unified instruction (MLOAD/MSTORE). This instruction simultaneously accesses multiple texels at different memory locations by computing their addresses using base coordinates and offsets, thereby reducing the number of instruction cycles and improving processing throughput without sacrificing access precision

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary computation of texel coordinates and offsets before the actual memory access. By pre-calculating the positions of multiple texels relative to a base location and storing these offsets in registers, the GPU can execute the merged load/store operation more efficiently without requiring multiple separate address computation cycles during the actual access phase

Inventive Principle:
Principle #10Preliminary action

2Productivity

If multiple separate instructions are used to access multiple texels, then each access operation can be individually optimized, but the overall device complexity and instruction overhead increase

Engineering Contradiction:
Improveinstruction execution efficiencyVSAvoidnumber of instructions required for texel operations
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple individual texel access instructions into a single MLOAD or MSTORE instruction that can handle multiple texels in one operation. This reduces the instruction count and simplifies the control flow while maintaining the ability to access multiple discrete memory locations through offset-based address computation

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The MLOAD/MSTORE instructions are designed to be universal and can access multiple texels regardless of their specific positions or offsets. The instruction handles various scenarios (different numbers of texels, different offset patterns) through a unified mechanism, reducing the need for multiple specialized instructions and simplifying the overall instruction set architecture

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250292482A1PERFORMING TEXEL ACCESS OPERATIONS ON MULTIPLE TEXELS RESPONSIVE TO EXECUTING A SINGLE INSTRUCTION BY GRAPHICS PROCESSING UNITS (GPUs)
Publication Date: 2025.09.18 QUALCOMM INC
  • US20250292482A1 patent drawing
  • US20250292482A1 patent drawing
  • US20250292482A1 patent drawing

AI summary

Performing texel access operations on multiple texels responsive to executing a single instruction by graphics processing units (GPUs) is disclosed herein. In some aspects, a GPU is configured to, responsive to execution of a single instruction, determine a first coordinate and a second coordinate of a location of a first texel of a texture. The GPU is further configured to determine a first offset corresponding to the first coordinate of the first texel and a second offset corresponding to the second coordinate of the first texel. The GPU is also configured to perform a texel access operation on each of the first texel and a second texel of the texture, wherein a location of the second texel is represented by a first sum of the first coordinate and the first offset, and a second sum of the second coordinate and the second offset.