Single Interconnect for Concurrent Memory Access
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Solution Overview
Problem
Existing shared memory systems in multithreaded processor systems suffer from high latency and overhead due to separate chip location and the need for semaphores or cache coherence, which hinder efficient parallel access operations.
Innovation Solution
A shared memory system where any addressable storage location is readable and writeable by concurrent threads, with a single-direction interconnect for data transfer from shared memory to processing engines, supporting both read and write operations, and utilizing a crossbar circuit for parallel data delivery and address routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate read and write interconnects are provided, then read and write operations can be performed independently, but chip area and power consumption increase
Solution Approach 1:
The patent merges separate read and write interconnects into a single bidirectional interconnect that handles both read and write operations. The interconnect circuit includes read ports and write ports that share the same physical communication path between the memory controller and memory array, reducing chip area while maintaining operational independence through logical separation of read and write channels.
Solution Approach 2:
The single interconnect is designed to serve multiple functions by supporting both read and write operations bidirectionally. The interconnect circuit can dynamically switch between read mode and write mode, allowing the same physical infrastructure to handle different types of memory access operations, thereby reducing overall system complexity and chip area.
2Reliability
If semaphores are used to prevent conflicting access requests, then memory access conflicts are resolved, but access latency increases due to sequential access
Solution Approach 1:
The patent segments the memory interface into multiple independent ports: read ports for simultaneous read operations and write ports for simultaneous write operations. This segmentation allows multiple threads to access memory in parallel without requiring semaphores, as each port operates independently with its own arbitration logic, thereby reducing access latency while maintaining conflict resolution.
Solution Approach 2:
The patent introduces an arbitration circuit as an intermediary between multiple threads and the memory interface. The arbitration logic manages access requests from multiple threads to read and write ports, allocating memory access resources fairly and efficiently without requiring thread-level semaphores. This intermediary handles conflict resolution at the interface level, preserving low-latency parallel access for compliant threads.
3Speed
If cached copies of shared memory are maintained in each processor, then access speed improves, but cache coherence overhead increases
Solution Approach 1:
The patent extracts the shared memory from the processor cores and places it in a separate, dedicated memory module with its own controller. This extraction eliminates the need for cached copies in each processor and the associated cache coherence overhead. The shared memory is directly accessible by multiple processors through the unified interconnect, providing fast access without requiring complex coherence protocols.
Solution Approach 2:
The shared memory system is designed to be self-servicing with its own dedicated controller that manages all access requests from multiple processors. The memory controller handles arbitration, data transfer, and conflict resolution internally, freeing the processors from the burden of maintaining cache coherence. This self-service approach simplifies the overall system while maintaining high access speeds.
Data Source
AI summary
A shared memory is usable by concurrent threads in a multithreaded processor, with any addressable storage location in the shared memory being readable and writeable by any of the threads. Processing engines that execute the threads are coupled to the shared memory via an interconnect that transfers data in only one direction (e.g., from the shared memory to the processing engines); the same interconnect supports both read and write operations. The interconnect advantageously supports multiple parallel read or write operations.