Single-Inverter Delay Line for Linear Delay Lock Loops
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Solution Overview
Problem
Conventional delay lines in delay lock loops suffer from non-linearity and duty cycle symmetry issues due to the use of two inverting gates in each delay stage, leading to excessive power consumption and limited adjustability, which affects the performance of phase mixers and clock signal synchronization.
Innovation Solution
A delay line with single NAND gates in each stage is used, combined with a phase inverter to maintain duty cycle symmetry and reduce the range over which the phase mixer interpolates, improving linearity and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If two inverting gates are used in each delay stage, then duty cycle symmetry is maintained, but power consumption increases and linearity deteriorates
Solution Approach 1:
The patent removes one inverting gate from each delay stage, extracting the excess inversion operation. A separate phase inverter is introduced to provide the necessary phase correction without the continuous power consumption of having two full inverting gates in each stage. This reduces power consumption while maintaining duty cycle symmetry through the dedicated phase inverter circuitry.
2Stability of the object's composition
If two inverting gates are used in each delay stage, then duty cycle symmetry is maintained, but linearity deteriorates
Solution Approach 1:
By removing one inverting gate from each delay stage, the patent reduces the non-linear phase shifts introduced by multiple inversion operations. The phase inverter is designed to provide controlled, linearizable phase correction, improving the overall linearity of the delay line while preserving duty cycle symmetry through its specific circuit implementation.
3Adaptability or versatility
If the number of gates in the delay line is increased, then delay adjustability improves, but power consumption increases
Solution Approach 1:
The patent implements dynamic control of delay stages through enable signals that selectively activate or deactivate individual stages based on the required delay setting. This allows a large number of gates to be available for fine delay adjustability while only activating the necessary subset during operation, thereby reducing power consumption compared to having all gates continuously active.
Solution Approach 2:
The delay line operates in a controlled manner where stages are periodically enabled or disabled based on the delay control signal. This periodic activation pattern allows the system to achieve high delay adjustability through many available stages while consuming power only when and where needed, rather than continuously across all stages.
4Adaptability or versatility
If the range of phase mixer interpolation is increased, then delay coverage is improved, but linearity deteriorates
Solution Approach 1:
The patent segments the delay line into multiple controllable stages that can be independently enabled or disabled. This segmentation allows the phase mixer to operate over a smaller, more manageable interpolation range at any given time, improving linearity. The overall delay coverage is maintained by selectively activating different segments based on the required delay setting, rather than requiring the phase mixer to cover the entire range simultaneously.
Data Source
AI summary
Locked loops, delay lines and methods for delaying signals are disclosed, such as a delay line and delay lock loop using the delay line includes a series of delay stages, each of which consists of a single inverting delay device. The inputs and outputs of a selected stage are applied to a phase inverter that inverts one of the signals and applies it to a first input of a phase mixer with the same delay that the other signal is applied to a second input of the phase inverter. The delay of the signals from the selected delay element are delayed from each other by a coarse delay interval, and the phase mixer interpolates within the coarse delay interval by fine delay intervals. A phase detector compares the timing of a signal generated by the phase interpolator to the timing of a reference clock signal applied to the delay line to determine the selected delay stage and a phase interpolation value.