Single Latch Write Driver Control Circuit for Memory Area Reduction
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Solution Overview
Problem
The existing write driver control circuits in semiconductor memory devices occupy a large area and consume excessive current due to the need for multiple latch units and delayed write driver enable signals, which complicates data transmission and increases power consumption during write operations.
Innovation Solution
A single-type latch-based write driver control circuit that compares and amplifies data from global input/output lines, outputs control signals, and precharges nodes to reduce area and current consumption, using a cross-coupled latch structure and inverters to manage voltage levels and latch signals efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple latch units and delayed write driver enable signals are used to control the write driver, then data transmission reliability is improved, but the area occupied by the write driver control circuit increases
Solution Approach 1:
The patent merges multiple latch units into a single latch unit that performs the latching function for both true and bar data lines. This is achieved by using a unified latch structure that responds to write driver enable signals to simultaneously control the state of both data lines, thereby reducing the overall circuit area while maintaining data transmission reliability through centralized control.
Solution Approach 2:
The single latch unit is designed to perform multiple functions: it latches both true and bar data, generates write driver control signals, and responds to write driver enable signals. This multi-functional design eliminates the need for separate latch units for each data line, reducing area occupation while preserving the reliability benefits of proper data latching.
2Reliability
If multiple latch units and delayed write driver enable signals are used to control the write driver, then data transmission reliability is improved, but current consumption increases
Solution Approach 1:
By combining multiple latch units into a single latch unit, the patent reduces the total number of active circuit elements that consume current. The unified latch structure processes both true and bar data through a single control mechanism, thereby reducing redundant current consumption while maintaining the reliability benefits of proper data latching and timing control.
Solution Approach 2:
The patent extracts and eliminates the delayed write driver enable signal mechanism, using a simplified enable signal approach that reduces unnecessary signal transitions and associated current consumption. By removing the delay circuitry and simplifying the enable signal generation, the circuit achieves reliable data transmission with lower power consumption.
3Loss of time
If a delayed write driver enable signal is used, then timing margin for data transmission is improved, but device complexity increases
Solution Approach 1:
The patent removes the delayed write driver enable signal mechanism from the circuit design. Instead of using delayed signals to achieve timing margins, the invention employs a unified latch unit that naturally provides timing control through its inherent latching behavior, thereby reducing device complexity while maintaining adequate timing margins for reliable data transmission.
Solution Approach 2:
The single latch unit is designed to self-regulate the timing of data latching and write driver control signal generation. By using the write driver enable signal directly without external delay circuits, the latch unit itself manages the timing requirements, eliminating the need for complex delay signal generation circuitry while ensuring proper timing margins are maintained.
Data Source
AI summary
A write driver control circuit controls operations of a write driver, which amplifies and transmits data of a pair of global input/output lines to a pair of local input/output lines in a write operation. A single type latch section compares states of first and second data of the pair of global input/output lines differentially inputted in a first status and then outputs a first output signal to a first output node; compares states of the first and second data differentially inputted in a second status and then outputs a second output signal to a second output node; and continuously latches states of the first and second output nodes before a precharge operation starts. A precharge controller equalizes and precharges the first and second output nodes in the precharge operation. An output section outputs first and second driver signals and first and second latch signals to control the write driver.