Single Level Routing via Polysilicon Resistor Bank Regions
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Solution Overview
Problem
The challenge in integrated circuit design is to reduce manufacturing costs by eliminating extra metal layers, which is complicated by the need to route electrical connections using a single level metal layer, as existing methods often require multiple layers and vias, increasing fabrication costs and complexity.
Innovation Solution
The design employs a resistor bank with a two-dimensional array of polysilicon resistor elements and a metal line in a single metal layer to create separate regions, allowing electrical connections to be made without crossing the metal line, thereby eliminating the need for additional metal layers and vias, using resistor elements to provide routing connections across rows and columns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple metal layers are used to facilitate electrical connections, then the circuit functionality is improved, but the manufacturing cost increases
Solution Approach 1:
The patent transitions from planar routing to three-dimensional routing by utilizing vertical vias to connect multiple metal layers. This allows electrical connections to be established in the vertical dimension, enabling complex circuit functionality while maintaining cost-effectiveness through single-poly routing architecture.
Solution Approach 2:
The patent implements a nested structure where resistor elements are integrated within the polysilicon layer itself, and metal interconnects are embedded within the resistor bank structure. This nesting allows routing connections to be formed through the resistor elements, eliminating the need for separate dedicated routing layers.
2Ease of manufacture
If a single metal layer is used for routing, then the manufacturing cost is reduced, but the routing capability is limited
Solution Approach 1:
The patent makes the polysilicon resistor layer serve multiple functions: it provides both the resistive elements and the routing interconnects. The metal interconnects embedded within the resistor bank perform dual functions of both connection and routing, eliminating the need for dedicated routing layers and enabling versatile connectivity with single-layer metal implementation.
Solution Approach 2:
The patent merges the resistor bank structure with the routing interconnect structure. Metal lines are embedded within the polysilicon resistor layer, combining the functions of resistance provision and electrical routing into a single integrated structure, thereby achieving both cost reduction and routing versatility.
Data Source
AI summary
An integrated circuit includes a substrate layer and a resistor bank in a polysilicon layer disposed on the substrate layer. The resistor bank includes a plurality of resistor elements having a body portion extending in a longitudinal direction. A metal line is disposed in a metal layer above the polysilicon layer to extend transverse to the longitudinal direction and across the body portion of a group of the plurality of resistor elements, thereby forming a first region of the resistor bank and a second region of the resistor bank. The first region is separated from the second region by the metal line. A resistor device having a predetermined resistance includes a subset of the resistor elements in the group electrically coupled together in the second region. The resistor device also includes first and second terminals located in the same first or second region of the resistor bank.