Single-Loop Duty Cycle Correction for Stable Clock Output
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional duty cycle correcting circuits in semiconductor integrated circuits are complex, prone to errors due to mismatches in clock edges, occupy large areas, consume significant power, and are difficult to improve or redesign for better performance.
Innovation Solution
A duty cycle correcting circuit with a duty ratio control signal generating block, a power supply block, and a signal processing block that detects the duty ratio of input clock signals and generates output clock signals by controlling voltage levels, using a single loop configuration to minimize errors and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional dual loop duty cycle correcting circuit is used to match rising edges of two clocks, then the duty ratio correction function is achieved, but the circuit structure becomes complicated and errors occur when rising edges are mismatched
Solution Approach 1:
The circuit is divided into three functional blocks: a duty ratio control signal generating block that detects duty ratio, a power supply block that supplies voltage to output nodes, and a signal processing block that controls voltage levels. This segmentation allows each block to perform a specific function independently, simplifying the overall structure while maintaining correction accuracy.
Solution Approach 2:
A duty ratio control signal (comprising multiple bits) is introduced as an intermediary between the duty ratio detection and the voltage level control. This control signal mediates the correction process by providing precise control information to the signal processing block, enabling accurate duty ratio correction without complex dual loop structures.
2Reliability
If a conventional duty cycle correcting circuit is implemented with dual loop configuration, then duty ratio matching is achieved, but the circuit occupies large area and consumes significant power
Solution Approach 1:
The invention extracts and eliminates the unnecessary dual loop configuration from conventional circuits. By using a single loop with a duty ratio control signal generating block that directly controls voltage levels, the circuit achieves duty ratio correction without the redundant structures that cause high power consumption and large area occupation.
Solution Approach 2:
The circuit changes the control parameter from complex phase matching in dual loop configurations to simple duty ratio detection and voltage level control. The duty ratio control signal comprising multiple bits provides precise control with simpler circuitry, reducing both power consumption and area while maintaining correction effectiveness.
3Reliability
If conventional duty cycle correcting circuits are designed with complex structures, then some level of duty ratio correction is achieved, but design changes to improve performance or reduce footprint are difficult to implement
Solution Approach 1:
The circuit employs a dynamic duty ratio control signal that can be adjusted based on detected duty ratio conditions. The signal processing block dynamically controls voltage levels of output nodes in response to the duty ratio control signal, allowing the circuit to adapt to different duty ratio requirements and enabling easy design modifications for performance improvement.
Data Source
AI summary
A duty cycle correcting circuit includes a duty ratio control signal generating block that detects a duty ratio of input clock signals and generates a duty ratio control signal comprising a plurality of bits, a power supply block that supplies a voltage to output nodes, and a signal processing block that controls voltage levels of the output nodes to correspond to voltage levels of the input clock signals in response to the plurality of bits of duty ratio control signals.