Single Mask MIM Capacitor Fabrication via Vertical Stacking

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Solution Overview

Problem

Conventional Metal-Insulator-Metal (MIM) capacitors with multiple conductive layers require multiple masks for formation, increasing fabrication cost and time, and may result in larger area usage due to lateral offset of conductive layers.

Innovation Solution

A method to form MIM capacitors using a single mask for both conductive and insulating layers, where conductive layers are aligned and vias are formed to couple with either odd or even numbered layers, reducing the need for multiple masks and potentially reducing area and cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple masks are used to form multiple conductive layers, then the conductive layers can be formed with proper connections, but the fabrication cost and time increase

Engineering Contradiction:
Improveconductive layer formationVSAvoidfabrication cost and time
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent combines multiple conductive layers into a single continuous conductive layer that extends across the entire capacitor structure. This eliminates the need for multiple separate masks and their associated alignment steps, directly reducing fabrication cost and time while maintaining proper electrical connections throughout the capacitor.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single continuous conductive layer serves multiple functions simultaneously: it acts as both the top and bottom electrodes for different capacitor sections, provides interlayer connections, and enables vias to access specific layers without requiring separate conductive layers for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Ease of operation

If conductive layers are laterally offset to enable via connections, then vias can connect to respective conductive layers, but the area increases

Engineering Contradiction:
Improvevia connectionVSAvoidcapacitor area
Core Design Contradiction:
Ease of operationVSArea of stationary object

Solution Approach 1:

The patent transitions from lateral offset (2D plane arrangement) to vertical stacking (3D arrangement). The single continuous conductive layer is positioned vertically above and below the insulator layers, with vias accessing specific layers through the vertical dimension. This eliminates the need for lateral offset while maintaining via connectivity, thereby reducing the horizontal area occupied by the capacitor.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If multiple conductive layers are formed, then capacitance density can be increased, but the fabrication complexity increases

Engineering Contradiction:
Improvecapacitance densityVSAvoidfabrication process complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent segments the capacitor into multiple functional sections (first capacitor section and second capacitor section) that share a common single continuous conductive layer. Each section has its own insulator layers and vias, but they utilize the same conductive layer, thereby achieving high capacitance density without requiring multiple separate conductive layers and their associated complex fabrication processes.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11502031B2Multiple layer metal-insulator-metal (MIM) structure
Publication Date: 2022.11.15 INTEL CORP
  • US11502031B2 patent drawing
  • US11502031B2 patent drawing
  • US11502031B2 patent drawing

AI summary

An apparatus is provided, which includes a stack of a first plurality of layers interleaved with a second plurality of layers. In an example, the first plurality of layers includes conductive material, and the second plurality of layers includes insulating material. In an example, the first plurality of layers includes an upper layer and lower layer. A first via may extend through at least a portion of the stack, where the first via may be in contact with the upper layer and the lower layer. A second via may extend through at least a portion of the stack, where the second via may be isolated from the upper layer and lower layer.