Single-Poly Floating Gate NVM Cell With Contact Control Gate
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges such as high voltage requirements for erase and program operations, significant area consumption, and increased bit cell size due to the use of silicon protection masks, which also lead to higher power consumption and reduced cycle durability.
Innovation Solution
A non-volatile memory cell design utilizing a silicide protection dielectric layer as the capacitive coupling dielectric between the control and floating gates, with control gate contacts positioned outside the active region, and a field plate metal overlapping the field oxide region, reducing the need for high voltages and minimizing area consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon protection mask is used to isolate the floating gate from the nitride layer, then charged loss is prevented and retention properties are improved, but the bit cell size increases due to dedicated distance allocation
Solution Approach 1:
The patent removes the silicon protection mask layer entirely from the structure. Instead of using a mask to prevent charged loss, the invention relies on the inherent properties of the silicide protection dielectric layer and the field dielectric region to provide isolation and prevent charge loss without requiring additional mask layers or dedicated distances.
Solution Approach 2:
The silicide protection dielectric layer serves multiple functions: it provides capacitive coupling between the control gate and floating gate, acts as a protection layer, and enables the control gate contact to be positioned outside the active region. This multi-functionality eliminates the need for separate silicon protection masks while maintaining retention properties.
2Reliability
If high voltage is applied between the control gate well and the body of the sense transistor for erase and program operations, then the memory operations can be performed, but a significant area is consumed to sustain the voltage drop and avoid junction breakdown
Solution Approach 1:
The silicide protection dielectric layer acts as an intermediary between the control gate and floating gate, enabling voltage application without direct contact. This intermediate layer allows for controlled voltage distribution and reduces the need for large voltage drops across junctions, thereby reducing the area required to sustain voltage during erase and program operations.
3Stress or pressure
If hot electrons and hot hole injection are used to lower program and erase voltages, then voltage requirements are reduced, but power consumption increases since only a small fraction of current is effectively injected
Solution Approach 1:
The patent changes the material parameter of the dielectric layer between the control gate and floating gate from conventional materials to a silicide protection dielectric layer. This material change enables more efficient charge injection with lower voltages while improving current utilization efficiency, thereby reducing both voltage requirements and power consumption simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces power consumption, minimizes bit cell size, and enhances cycle durability by optimizing voltage requirements and capacitive coupling, while maintaining efficient data storage and retrieval.
Implementation Method 1
utilize a silicide protection dielectric layer as the capacitive coupling dielectric of the control gate and floating gate of the floating gate transistor
Implementation Method 2
a dielectric layer interposed between the control gate and the floating gate
Data Source
Figure 1A
Figure 1B
Figure 2
AI summary
A cost-effective solution to implement a non-volatile memory cell (100) based on floating gate transistor (T1) including a floating gate (112) that overlies an active region (106) and a field region (105, 108) of a semiconductor substrate (104): Single Poly Floating Gate NVM bitcell. The control gate terminal is made at least in part of a metallic material and it is implemented with contact plug/s (Contact Control Gate) or metal field plate (152) separated by the floating gate using commonly present in CMOS process silicide protection dielectric layer SIPROT stack (oxide(s) and nitride(s)).