Single Poly EPROM Double Control Gate Area Reduction
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Solution Overview
Problem
Conventional Single Poly EPROM devices require a dedicated select transistor to protect the drain during programming, leading to increased area usage in memory arrays due to the need for high voltage select transistors for each memory cell.
Innovation Solution
The Single Poly EPROM device incorporates an additional gate above the floating gate, connected to a tri-state buffer that controls the voltage to prevent unintentional charging or discharging, eliminating the need for a select transistor by using Fowler-Nordheim tunneling for programming and ensuring the floating gate is not unintentionally programmed or erased.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated select transistor is used to protect the drain during programming, then the reliability of the EPROM device is improved, but the area of the memory array increases
Solution Approach 1:
The invention extracts the protection function from the dedicated select transistor and relocates it to the control gate. By applying high voltage selectively to the control gate, the device can protect itself from unintentional programming without requiring external select transistors, thereby eliminating the area overhead while maintaining reliability
Solution Approach 2:
The control gate is given a dual function: it serves both as the control electrode for the floating gate and as a select mechanism for protecting the drain. This multi-functionality eliminates the need for separate select transistors, reducing the memory array area while maintaining the protection function
2Productivity
If high voltage is applied to the drain during erasing, then the programming function is improved, but unintentional programming of unselected cells occurs
Solution Approach 1:
The invention applies preliminary anti-action by using the control gate to establish a protective potential barrier before high voltage is applied to the drain. This pre-established barrier prevents charge carriers from reaching the floating gate of unselected cells, counteracting the harmful effect of high voltage on neighboring cells
Solution Approach 2:
The control gate acts as an intermediary element between the drain and the floating gate. It mediates the effect of high drain voltage by providing an additional potential barrier that prevents direct interaction between the drain and floating gate in unselected cells, thereby preventing unintentional programming
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the area required in memory arrays by eliminating the need for high voltage select transistors, allowing for efficient programming and erasure of Single Poly EPROM devices without risking unintentional changes, and allows for a significant reduction in the total area of the memory array.
Implementation Method 1
Single Poly EPROM devices can be programmed either through hot carrier injection or Fowler-Nordheim tunneling
Data Source
AI summary
A single poly EPROM comprises a floating gate (10), a control gate (12), a source (16) and a drain (18). The control gate (12) is positioned laterally of a channel between the source (16) and the drain (18). The floating gate (10) is positioned above the channel and above the control gate (12). The single poly EPROM device further comprises an additional gate (40) above the floating gate (10) and a control. The control is connected to the additional gate (40) for controlling a voltage at the floating gate (10) in order to prevent the floating gate (10) from being unintentionally charged or discharged.