Single-Poly Memory Cell Programming via Dielectric Breakdown
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Solution Overview
Problem
Conventional single-poly non-volatile memory devices face challenges in miniaturization due to insufficient tunnel oxide thickness, requiring higher operational voltages that stress gate oxide reliability and occupy more chip area, and existing solutions either complicate the design or require additional transistors.
Innovation Solution
A single-poly, single-transistor non-volatile memory cell unit with a conductive gate on a P well, a gate dielectric layer, and N type drain and source regions, where the P well is connected to a P well voltage, the source region to a source voltage higher than the P well voltage, and the drain region to a drain voltage relative to the P well voltage, creating strong inversion and allowing programming and reading with reduced voltage and simplified design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single-poly non-volatile memory uses floating gate structure with ONO insulation layer, then charge storage capability is improved, but device complexity and manufacturing cost increase due to additional thermal budget and process adjustments
Solution Approach 1:
The patent extracts and removes the floating gate structure and ONO insulation layer from the conventional single-poly NVM architecture. By eliminating these components, the device achieves non-volatile memory functionality using only a single polysilicon gate, thereby reducing manufacturing process complexity and eliminating the need for additional thermal budget while maintaining charge storage capability through alternative mechanisms
Solution Approach 2:
The single polysilicon gate structure performs multiple functions: it serves as both the control gate for transistor operation and the charge storage element for non-volatile memory functionality. This multi-functional design eliminates the need for separate floating gate and control gate structures, simplifying the device architecture and manufacturing process
2Area of stationary object
If single-poly non-volatile memory is miniaturized for 90 nm scale, then chip area usage is improved, but tunnel oxide thickness becomes insufficient requiring higher operational voltages that stress gate oxide reliability
Solution Approach 1:
The patent changes the operational voltage parameters to optimized levels that work effectively with the single-poly structure. By carefully selecting and adjusting voltage levels for programming and reading operations, the device achieves reliable operation with miniaturized dimensions without subjecting the gate oxide to excessive stress, thus maintaining reliability while reducing chip area
3Ease of manufacture
If conventional single-poly NVM uses higher operational voltages for programming, then programming capability is improved, but power consumption and gate oxide stress increase
Solution Approach 1:
The patent optimizes the programming voltage parameters to achieve effective programming capability with reduced voltage levels compared to conventional single-poly NVM. By carefully controlling the voltage applied to the single polysilicon gate during programming operations, the device achieves reliable charge storage while minimizing power consumption and reducing stress on the gate oxide structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the On-Off current margin, improves reliability, and simplifies chip design by allowing for more efficient programming and reading operations within advanced logic processes, achieving higher reliability and reduced chip area usage.
Implementation Method 1
the gate voltage VG will discharge through a leakage path formed in the gate dielectric layer
Data Source
AI summary
A method for operating a single-poly, single-transistor (1-T) non-volatile memory (NVM) cell. The NVM cell includes a gate on a P substrate, a gate dielectric layer, an N drain region and an N source region. N channel is defined between the N drain region and N source region. The NVM cell is programmed by breaking down the gate dielectric layer. To read the NVM cell, a positive voltage is provided to N drain region, a positive voltage is provided to the gate, and grounding the N source region and the P substrate.