Single-Poly Non-Volatile Memory Cell for Low Power Programming
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges in achieving low power consumption and flexibility in programming modes, particularly in supporting page or byte programming and being compatible with various substrates while maintaining high endurance.
Innovation Solution
A non-volatile memory cell design incorporating a floating-gate transistor, a select transistor, and a coupling structure, fabricated using a CMOS process, which allows for low power consumption and programming by page or byte, with operations optimized for read, program, and erase modes, and suitable for different substrate types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional non-volatile memory designs are used, then programming and erasing functions can be achieved, but power consumption increases and flexibility in programming modes is reduced
Solution Approach 1:
The memory cell is segmented into distinct functional components: a floating-gate transistor for charge storage, a select transistor for access control, and a coupling structure for data retention. This segmentation allows independent optimization of each component for low power consumption while maintaining programming flexibility through selective activation of different components in different modes.
Solution Approach 2:
The memory cell design incorporates multi-functionality by enabling both page programming and byte programming modes through the same basic cell structure. The coupling structure between the floating-gate transistor and select transistor allows the cell to operate in different programming modes without requiring separate dedicated circuits, thus achieving versatility while maintaining low power consumption.
2Reliability
If additional electric circuits are added to support programming and erasing operations, then memory functionality is improved, but device complexity and chip area increase
Solution Approach 1:
The patent merges the programming and erasing functions into a unified cell structure where the floating-gate transistor and select transistor work together to perform both operations. The coupling structure integrates the data retention function with the access control function, eliminating the need for separate dedicated circuits for each operation and reducing overall device complexity.
Solution Approach 2:
The memory cell is designed with universal functionality where the same basic structure supports multiple operations including page programming, byte programming, and erasing. This multi-functionality is achieved through the coupling structure that allows different operation modes to be implemented using the same physical components, thereby reducing device complexity while maintaining comprehensive memory functionality.
3Ease of manufacture
If single-poly non-volatile memory is used, then processing cost is reduced and CMOS compatibility is achieved, but power consumption and programming flexibility are compromised
Solution Approach 1:
The patent applies local quality by optimizing specific regions of the single-poly memory cell for different functions. The floating-gate transistor region is optimized for charge storage with low leakage, while the select transistor region is optimized for access control. The coupling structure is locally optimized to enable low-power operation modes. This localized optimization allows the single-poly structure to achieve low power consumption and programming flexibility while maintaining CMOS compatibility and ease of manufacture.
Data Source
AI summary
A non-volatile memory cell includes a floating-gate transistor, a select transistor, and a coupling structure. The floating-gate transistor is deposited in a P-well and includes a gate terminal coupled to a floating gate which is a first polysilicon layer, a drain terminal coupled to a bit line, and a source terminal coupled to a first node. The select transistor is deposited in the P-well and includes a gate terminal coupled to a select gate which is coupled to a word line, a drain terminal coupled to the first node, and a source terminal coupled to the source line. The floating-gate transistor and the select transistor are N-type transistors. The coupling structure is formed by extending the first polysilicon layer to overlap a control gate, in which the control gate is a P-type doped region in an N-well and the control gate is coupled to a control line.