Single Poly NVM Bitcell Design for Compact Memory Arrays
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Solution Overview
Problem
Conventional single poly NVM designs face challenges in reducing bitcell size while maintaining data retention and reliability, often resulting in increased chip size and cost due to the need for additional processing steps and potential damage to the gate oxide during erase operations.
Innovation Solution
A compact PMOS EEPROM bitcell design that uses a p-type doped floating gate layer forming a coupling capacitor over a p-well, eliminating the need for n-well to n-well spacing and allowing for efficient configuration in a memory array, with a shared n-well for each bitcell, utilizing Fowler-Nordheim tunneling for erase operations without additional process costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single poly NVM designs use electrical isolation between different wells, then data retention and reliability are maintained, but bitcell size increases significantly
Solution Approach 1:
The patent merges the isolation function into the well structure itself by using a shared n-well that is junction-isolated from the substrate, eliminating the need for separate isolation structures between wells. This allows adjacent bitcells to share the same well region, dramatically reducing bitcell area while maintaining electrical isolation through the substrate junction.
Solution Approach 2:
The shared n-well serves multiple functions simultaneously: it provides electrical isolation from the substrate through junction isolation, serves as the control gate for the floating gate transistor, and enables voltage sharing between adjacent bitcells. This multi-functionality reduces the number of separate components needed, shrinking bitcell size.
2Reliability
If additional processing steps are added to construct floating gate or control gate features, then NVM functionality is achieved, but manufacturing cost increases
Solution Approach 1:
The patent combines the control gate and floating gate into a single polysilicon layer structure. The control gate is formed as part of the same polysilicon deposition and doping process that creates the floating gate, eliminating separate processing steps for control gate formation and reducing overall manufacturing complexity.
Solution Approach 2:
The shared n-well structure serves as both the isolation mechanism and the control gate, eliminating the need for a separate control gate electrode. This reduces the number of material layers and processing steps required compared to conventional designs that use distinct control gate structures.
3Ease of operation
If band to band tunneling of hot holes is used to erase the memory bitcell, then erase capability is achieved, but gate oxide is damaged and device reliability is reduced
Solution Approach 1:
The patent introduces the shared n-well as an intermediary structure that enables Fowler-Nordheim tunneling erase operations. By applying voltage to the shared n-well, electrons can be extracted from the floating gate through the gate oxide without requiring band-to-band tunneling of hot holes, thus achieving erase capability while preserving gate oxide integrity.
Solution Approach 2:
The patent changes the erase mechanism from band-to-band tunneling (which requires high electric fields that damage oxide) to Fowler-Nordheim tunneling (which uses quantum mechanical tunneling at lower fields). This parameter change in the physical mechanism allows erase operations to proceed without compromising device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a compact bitcell footprint with improved reliability and data retention, reducing chip size and cost while maintaining electrical program and erase capabilities, and mitigating over-erasure and achieving better erase uniformity.
Implementation Method 1
a coupling capacitor formed over a p-well region to include a first capacitor plate formed with a part of the p-type floating gate layer, a capacitor dielectric layer, and a second capacitor plate formed with an underlying portion of the p-well region
Implementation Method 2
charge on the floating gate may be erased using a Fowler-Nordheim tunneling mechanism by applying a first relatively high voltage to the shared n-well region
Data Source
AI summary
A single-poly non-volatile memory includes a PMOS select transistor (210) formed with a select gate (212), and P+ source and drain regions (211, 213) formed in a shared n-well region (240), a serially connected PMOS floating gate transistor (220) formed with part of a p-type floating gate layer (222) and P+ source and drain regions (221, 223) formed in the shared n-well region (240), and a coupling capacitor (230) formed over a p-well region (250) and connected to the PMOS floating gate transistor (220), where the coupling capacitor (230) includes a first capacitor plate formed with a second part of the p-type floating gate layer (222) and an underlying portion of the p-well region (250).