Single Port Cache with Multiplexed Dual Access
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Solution Overview
Problem
Existing microprocessor caching systems are inflexible and inefficient, as they often require separate data and program caches, which can lead to reduced bandwidth and increased power consumption due to the need for dual-ported SRAMs and complex control logic, while also being larger than needed for many applications.
Innovation Solution
A single ported cache system that allows simultaneous access to both data and program instructions using multiplexers and SRAMs with tristate outputs, enabling full bandwidth utilization without the need for dual-ported memory or separate caches, while maintaining a compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate data and program caches are used, then bandwidth for simultaneous accesses is improved, but device complexity and power consumption increase due to dual-ported SRAMs and duplicate control logic
Solution Approach 1:
The patent combines separate data and program caches into a unified single cache structure with shared control logic. The cache controller manages both data and instruction accesses through a single port, eliminating the need for dual-ported SRAMs and duplicate control units while maintaining the ability to serve both cache types simultaneously through intelligent arbitration and way-prediction mechanisms.
Solution Approach 2:
The single cache structure is designed to serve multiple functions - it can operate as a data cache, an instruction cache, or a combination of both depending on the operational mode. The cache ways can be dynamically allocated and dedicated to different functions (data vs. program) through software configuration, allowing the same hardware structure to adapt to different application requirements without requiring separate specialized caches.
2Productivity
If dual ported SRAMs are used for simultaneous data and program access, then bandwidth is improved, but chip area and power consumption increase
Solution Approach 1:
The patent merges the functionality of dual ported SRAMs into a single ported cache structure. By using a single cache with intelligent arbitration, way dedication, and prediction logic, the system achieves simultaneous data and program access capabilities without requiring the physical duplication of memory ports and associated control logic, thereby reducing chip area while maintaining bandwidth performance.
3Area of stationary object
If combined data and program cache is used, then chip area is reduced, but bandwidth is limited to one-half of separate caches due to single access capability
Solution Approach 1:
The patent introduces dynamic mechanisms including way-prediction logic and dynamic way allocation that allow the cache to adaptively respond to access patterns. The system can predict which cache ways will be needed for data versus program accesses and pre-configure the cache structure accordingly, enabling simultaneous servicing of both access types through dynamic reconfiguration rather than static single-access limitation.
Solution Approach 2:
The cache system performs preliminary actions by dedicating specific cache ways to data or program functions in advance based on predicted access patterns. This pre-configuration allows the cache to be optimally prepared to handle simultaneous data and program accesses without conflict, effectively doubling the bandwidth compared to a simple single-access cache while maintaining a compact unified structure.
4Productivity
If separate data and program caches are used, then bandwidth is improved, but the cache size is larger than needed for many applications
Solution Approach 1:
The unified cache structure provides multi-functionality by serving both data and program caching needs within a single configurable memory space. The cache can be dynamically allocated to provide different portions for data versus program storage based on application requirements, allowing the total cache size to be optimized for each specific application rather than requiring fixed large separate caches for all scenarios.
Data Source
AI summary
A method and system for accessing a single port multi-way cache includes an address multiplexer that simultaneously addresses a set of data and a set of program instructions in the multi-way cache. Duplicate output way multiplexers respectively select data and program instructions read from the cache responsive to the address multiplexer.