Single-Rail Scan Multiplexer for Dual-Rail Asynchronous Logic

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Solution Overview

Problem

Design for test (DFT) circuitry in synchronous and asynchronous processors incurs significant power consumption and chip area overhead due to unnecessary cycling and propagation delays, particularly in dual-rail delay insensitive asynchronous logic (DIAL) processors.

Innovation Solution

Implementing a single-rail selector input logic multiplexer with Boolean AND-OR gates instead of dual-rail threshold gates reduces power consumption and chip area by avoiding cyclic switching during the propagate data and propagate null phases, allowing for efficient testing while minimizing unnecessary power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dual-rail threshold gates are used in DIAL processors, then delay insensitivity and robustness are improved, but power consumption and chip area increase significantly

Engineering Contradiction:

Improvedelay insensitivityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The processor is segmented into two distinct operational modes: a low-power standby mode using single-rail logic for control signals, and an active dual-rail mode for data processing. This segmentation allows the system to use complex dual-rail threshold gates only when necessary for delay-insensitive operation, while using simpler single-rail logic otherwise, thereby reducing overall power consumption while maintaining reliability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention changes the operational parameters of the logic gates by implementing a hybrid approach where control signals use single-rail logic with different voltage levels and timing characteristics compared to dual-rail data paths. This parameter change allows the system to achieve delay insensitivity through careful voltage level design and timing control rather than relying exclusively on complex dual-rail threshold gate structures, thus reducing power consumption.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If dual-rail threshold gates are used in DIAL processors, then delay insensitivity is improved, but chip area overhead increases

Engineering Contradiction:

Improvedelay insensitivityVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The processor architecture segments functionality between single-rail control logic and dual-rail data paths, using complex threshold gate structures only where delay insensitivity is critical for data processing, while control and configuration signals use simpler single-rail logic. This reduces the overall density of threshold gates on the chip, thereby reducing chip area while maintaining delay insensitivity where required.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The single-rail control logic is designed to be multi-functional, handling both control signal generation and configuration tasks that would otherwise require separate dual-rail control paths. This universality reduces the total number of threshold gates needed, thereby reducing chip area overhead while maintaining the delay-insensitive operation of the processor.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Difficulty of detecting and measuring

If DFT circuitry is added to asynchronous processors, then testability is improved, but power consumption and propagation delay increase

Engineering Contradiction:

ImprovetestabilityVSAvoidpower consumption

Core Design Contradiction:

Difficulty of detecting and measuringVSUse of energy by stationary object

Solution Approach 1:

The testability features are merged with the existing single-rail control logic infrastructure rather than being implemented as separate dual-rail control paths. The scan chain and control signal generation share the same single-rail logic gates and signal paths, eliminating the need for duplicate dual-rail control circuitry. This merging reduces the overall power consumption and propagation delay while maintaining full testability through the integrated control logic.

Inventive Principle:

Principle #5Merging (Combining)

4Difficulty of detecting and measuring

If DFT circuitry is added to asynchronous processors, then testability is improved, but propagation delay increases

Engineering Contradiction:

ImprovetestabilityVSAvoidpropagation delay

Core Design Contradiction:

Difficulty of detecting and measuringVSLoss of time

Solution Approach 1:

The testability circuitry is merged with the single-rail control logic, sharing the same signal paths and timing characteristics. This integration ensures that test signals propagate through the same optimized single-rail paths as normal control signals, avoiding the additional propagation delay that would result from separate dual-rail control paths. The merged architecture maintains fast signal propagation while providing comprehensive testability.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS10338930B2Dual-rail delay insensitive asynchronous logic processor with single-rail scan shift enable

Publication Date: 2019.07.02 SAMSUNG ELECTRONICS CO LTD

AI summary

There is disclosed a self-timed processor. The self-timed processor includes combinatorial logic comprising multi-rail delay insensitive asynchronous logic (DIAL) to output one or more multi-rail data values to a multiplexer. It also includes a test pattern input to output a test pattern bit stream of multi-rail test data values to the multiplexer. The multiplexer has Boolean logic to output one or more multi-rail multiplexed values to a latch. The multiplexer also has a single rail selector input to select whether the multi-rail multiplexed values are the multi-rail data values or the multi-rail test data values.