Single-Rail SRAM Global Data Line With Automatic Three-State Drivers

The patent divides the SRAM device into multiple sub-arrays (Block 0 through Block 3) with separate bit lines for each sub-array. This segmentation allows each sub-array to be independently accessed through its own bit line, eliminating the need for a single heavy-load global data line that spans all sub-arrays, thereby reducing power consumption while maintaining data access capability.

The patent transitions from a single-rail global data line approach to a multi-rail approach where multiple bit lines operate in parallel across different sub-arrays. This dimensional expansion allows simultaneous data access across multiple sub-arrays without creating a single bottleneck, reducing the load on any individual data line and lowering overall power consumption.

By segmenting the data transmission paths into separate bit lines for each sub-array, the patent eliminates the long propagation path of a single global data line spanning all sub-arrays. Each sub-array can be accessed through its own local bit line, significantly reducing propagation delay and improving timing performance while maintaining comprehensive data transmission coverage.

The patent implements pre-charging of bit lines before data access operations. This preliminary action ensures that data lines are already in the appropriate state before data transmission begins, reducing setup time and improving overall timing performance by eliminating delays associated with state transitions during data access.