Multi-Power-Domain Control Circuit With Single-Signal Isolation
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Solution Overview
Problem
Existing power management circuits for integrated circuits with multiple power domains face challenges in reducing power consumption and chip area, as they require multiple control signals for power isolation, leading to increased power consumption and potential damage from incorrect power-on sequences.
Innovation Solution
A power management circuit that includes an inverter circuit and a latch circuit, along with a level shifter and output buffer, to perform power-on control and power isolation using a single control signal, allowing zero quiescent current consumption and tolerant power-on/off sequences across different power domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple control signals are used for power isolation between power domains, then power isolation reliability is improved, but power consumption and device complexity increase
Solution Approach 1:
The patent combines multiple control signals into a single control signal that can simultaneously control power isolation between multiple power domains. The power management circuit uses this single control signal to manage power-on sequences and isolation states across different power domains, thereby reducing the number of control signals while maintaining isolation reliability.
Solution Approach 2:
The single control signal is designed to serve multiple functions: it controls power-on sequencing, manages power isolation between domains, and indicates power status across different power domains. This multi-functional approach eliminates the need for separate control signals for each power domain, reducing overall power consumption and circuit complexity.
2Reliability
If multiple control signals are used for power isolation between power domains, then power isolation reliability is improved, but chip area increases
Solution Approach 1:
The patent merges multiple control signal lines into a single control signal line that can address multiple power domains. This consolidation reduces the number of signal routing lines required on the chip, thereby reducing the overall chip area while maintaining the ability to perform power isolation between domains.
Solution Approach 2:
The single control signal is designed to universally control power isolation across multiple power domains, eliminating the need for dedicated control signal lines for each domain. This reduces the routing complexity and area required for control signal distribution across the chip.
3Productivity
If power domains are activated without proper sequencing, then productivity is improved, but circuit damage risk increases
Solution Approach 1:
The power management circuit performs preliminary actions by monitoring the power status of each domain and controlling the activation sequence. Before allowing a power domain to be activated, the circuit ensures that the controlling signal is ready and that proper isolation states are established, preventing premature activation that could lead to circuit damage.
Solution Approach 2:
The circuit uses feedback mechanisms to monitor the power status of different domains and adjust the control signals accordingly. The control signal is generated based on the power status feedback, ensuring that power domains are activated in the correct sequence and that isolation is maintained until appropriate, thereby preventing circuit damage while enabling fast activation.
Data Source
AI summary
A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.