Single-Stage Frequency Multiplier With Mixed-Mode Harmonic Generation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing frequency multipliers require multiple stages and buffering, leading to large area requirements and high power consumption, especially at mmWave frequencies, and generate undesired harmonics that complicate signal processing due to their proximity to desired harmonics.
Innovation Solution
A stacked single-stage frequency multiplier using common mode and differential mode mixing, which eliminates the need for buffer stages by reusing current and optimizing biasing, allowing for independent control over bias points and improved conversion gain, thereby generating higher harmonics with reduced power consumption and increased spacing between desired and undesired harmonics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple multiplication stages are used to generate higher harmonics, then the desired harmonic frequency is achieved, but the area and power consumption increase significantly
Solution Approach 1:
The patent combines multiple multiplication functions into a single stage by using a mixer that directly generates higher harmonics (e.g., 6×) from the input signal without requiring sequential 2× and 3× stages. This merging of functions eliminates the need for multiple separate multiplier circuits and their associated buffering, significantly reducing the total area while achieving the same frequency multiplication goal.
Solution Approach 2:
The mixer circuit is designed to perform multiple functions simultaneously: it acts as both the frequency mixing element and the harmonic generator for multiple multiplication factors. By configuring the mixer with specific biasing and loading conditions, a single circuit can generate multiple harmonics (2×, 3×, 4×, etc.) without requiring separate dedicated circuits for each multiplication stage.
2Speed
If multiple multiplication stages with buffering are implemented, then higher harmonics are generated, but power consumption increases particularly at mmWave frequencies
Solution Approach 1:
By merging multiple multiplication stages into a single direct harmonic generation stage, the patent eliminates the power-consuming buffer amplifiers that would be required between stages. The single-stage mixer directly drives the output, removing the need for intermediate buffering and significantly reducing total power consumption, especially at high mmWave frequencies where buffer power requirements are substantial.
Solution Approach 2:
The patent maintains continuous useful action by having the mixer directly generate and output the desired harmonic without interruption by buffer stages. This continuous operation eliminates the power losses associated with multiple conversion stages and their buffering, allowing the useful signal generation to proceed efficiently from input to output in a single uninterrupted process.
3Speed
If conventional multi-stage multiplication is used, then higher harmonics are generated, but undesired harmonics appear close to the desired harmonic complicating signal processing
Solution Approach 1:
The patent applies local quality by optimizing specific parameters of the mixer circuit (such as biasing conditions, loading impedance, and resonator tuning) to enhance the generation of the desired harmonic while suppressing adjacent unwanted harmonics. By carefully controlling the local characteristics of the mixer at the target frequency, the circuit achieves selective harmonic generation with improved spectral purity and reduced interference from nearby spurious signals.
4Area of stationary object
If a single stage frequency multiplier is used, then area and power are reduced, but generating higher harmonics becomes more difficult
Solution Approach 1:
The patent employs parameter changes by adjusting key mixer parameters (bias currents, voltage swing, loading Q, resonator frequencies) to enable a single stage to generate higher harmonics effectively. By optimizing these parameters, the mixer's conversion gain at the desired harmonic frequency is maximized while maintaining stability and linearity, making single-stage high-order multiplication practical without requiring complex multi-stage architectures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a compact, power-efficient frequency multiplier that generates higher multiple harmonics with improved harmonic rejection, reducing area and power requirements while maintaining efficient operation at higher frequencies.
Implementation Method 1
a mixer section coupled to the input section by a common mode node that forms a path for a common mode current to flow to the mixer section, the mixer section also magnetically coupled to the common mode node
Implementation Method 2
an output section magnetically coupled to the mixer section. The output section is configured to generate, in response to the input signal, an output signal
Implementation Method 3
the mixer section magnetically coupled to the input section and directly capacitively coupled to the input section through a capacitor in a signal current path
Data Source
AI summary
A frequency multiplier includes an input section having inputs to receive an input signal having an input frequency, a mixer section, and an output section magnetically coupled to the input section and generating an output signal in response to the input signal. The mixer section may be coupled to the input section by a common mode node forming a path for a common mode current to flow to the mixer section and be magnetically coupled to the common mode node. The input section may generate a signal current, and the mixer section may be magnetically coupled to the input section and be directly capacitively coupled to the input section through a capacitor in a signal current path. The mixer section may have differential inputs capacitively coupled to the input section and also be coupled to the input section through a current path. A current helper section may be coupled to the current path.