Single-Stage Frequency Multiplier With Mixed-Mode Harmonic Separation
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Solution Overview
Problem
Existing frequency multipliers require multiple stages and buffering, leading to a large footprint and high power consumption, especially in the mmWave frequency range, and generate undesired harmonics that complicate signal processing due to their proximity to desired harmonics.
Innovation Solution
A stacked single-stage frequency multiplier using common mode and differential mode mixing, which generates a desired harmonic with increased spacing from undesired harmonics by reusing common mode current and applying differential switching voltage, eliminating the need for buffer stages and optimizing biasing for improved conversion gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple stages and buffering are used in frequency multipliers, then frequency multiplication capability is improved, but device area and power consumption increase
Solution Approach 1:
The patent combines multiple frequency multiplication stages into a single integrated stage that simultaneously performs both 2× and 3× multiplication functions. The mixer section integrates the 2× multiplier and 3× multiplier circuits in a unified structure, eliminating the need for separate stages and intermediate buffering, thereby reducing device area while maintaining frequency multiplication capability
Solution Approach 2:
The single stage frequency multiplier is designed to perform multiple functions: it generates both 2× and 3× frequency multiplication outputs, provides buffering functionality internally, and handles both differential and common mode signals. This multi-functional design replaces what would traditionally require multiple separate components, reducing overall device area
2Productivity
If multiple stages and buffering are used in frequency multipliers, then frequency multiplication capability is improved, but power consumption increases
Solution Approach 1:
By merging multiple frequency multiplication stages into a single integrated stage with shared buffering resources, the patent eliminates redundant power-consuming elements. The unified mixer section and common buffer structure reduce the total number of active components, thereby lowering overall power consumption while maintaining frequency multiplication capability
Solution Approach 2:
The single stage multiplier performs multiple frequency multiplication functions and provides internal buffering in one power-efficient structure. This multi-functional design avoids the need for separate powered stages and buffers, reducing total power consumption
3Productivity
If traditional frequency multiplication approaches are used, then frequency multiplication is achieved, but undesired harmonics are generated close to desired harmonics
Solution Approach 1:
The patent employs different mixing modes (differential mode and common mode) in different parts of the circuit to selectively generate and suppress specific harmonics. The differential mode mixing generates odd-order harmonics while common mode mixing generates even-order harmonics, allowing selective extraction of desired harmonics and suppression of undesired ones through tailored circuit configurations
Solution Approach 2:
The patent uses asymmetric circuit configurations where the differential and common mode paths are deliberately designed with different characteristics. This asymmetry causes undesired harmonics to appear at different frequency locations or with different amplitudes, making them easier to filter or reject while preserving desired harmonics
4Productivity
If undesired harmonics are generated close to desired harmonics, then frequency multiplication is achieved, but signal processing complexity increases
Solution Approach 1:
By using different mixing modes in different circuit sections, the patent creates a frequency spectrum where desired and undesired harmonics are spatially separated in the frequency domain. This natural separation reduces the complexity of subsequent signal processing and filtering operations
Solution Approach 2:
The asymmetric design of differential and common mode paths creates distinct harmonic patterns that simplify signal processing. The deliberate frequency spacing of harmonics reduces interference and simplifies the design of subsequent filtering and selection circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces the footprint and power consumption while effectively rejecting unwanted harmonics, achieving a compact and efficient frequency multiplication with well-spaced desired and undesired harmonics, thereby improving signal processing efficiency.
Implementation Method 1
a common mode node that forms a path for a common mode current (e.g., I4f0) to flow to the mixer section
Implementation Method 2
which is electrically coupled to the input section to generate a differential switching voltage (VDM) that is applied at inputs of the mixer section, the common mode current having a dominate frequency (e.g., 4f0) that is a first multiple (e.g., 4) of the input frequency (f0)
Implementation Method 3
The output section, which is magnetically coupled to the mixer section, is configured to generate, in response to the input signal, an output voltage (Vow) having a dominate frequency (e.g., 6f0)
Data Source
AI summary
A frequency multiplier includes an input section to receive a quadrature phase input signal having an input frequency, a mixer section coupled to the input section by a common mode node that forms a path for the common mode signal current to flow to the mixer section and magnetically coupled to the common mode node or capacitively coupled to the input section to generate a differential switching voltage at odd multiples of twice the input frequency, which switching voltage is applied to inputs of the mixer section, and an output section magnetically coupled to the mixer section, the output section being configured to generate an output voltage having a dominate frequency and sub-dominate frequencies spaced apart by the first multiple, the dominate frequency of the output voltage being a second multiple of the input frequency, where the second multiple is greater than the first multiple. Various arrangements are provided.