Single-Well Upper Layer in Multi-Layer Memory Devices
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Solution Overview
Problem
The need for deep wells in memory cell regions of multiple-layered semiconductor devices increases manufacturing costs and limits device density, as they require complex well configurations to isolate peripheral regions during programming and erase operations.
Innovation Solution
Implementing a multiple-layered semiconductor device configuration where upper layers have a single well in the memory cell region, reducing the number of manufacturing steps and increasing vertical density by eliminating the need for a deep well, thus simplifying the fabrication process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep wells are formed in the memory cell region of each layer to isolate peripheral regions during program and erase operations, then peripheral region isolation is achieved, but manufacturing costs increase and device density is limited
Solution Approach 1:
The device is divided into two distinct layers: the first layer maintains the triple-well configuration (deep well, pocket well, and peripheral well) for proper isolation during program and erase operations, while the second layer uses a simplified single-well configuration. This segmentation allows each layer to have the appropriate complexity for its function, resolving the contradiction between isolation reliability and device complexity.
Solution Approach 2:
Different well configurations are applied to different layers based on their specific requirements. The first layer (closer to the substrate) uses the complete triple-well structure where isolation is critical, while the second layer (upper layer) uses a simplified single-well structure where isolation can be achieved through other means. This local differentiation optimizes both isolation performance and manufacturing complexity.
2Reliability
If deep wells are formed in the memory cell region of each layer, then peripheral region isolation is achieved, but manufacturing costs increase
Solution Approach 1:
The manufacturing process is segmented into two parts: forming deep wells only in the first layer rather than in both layers. This reduces the total number of well formation steps, decreases process complexity, and lowers manufacturing costs while still achieving the necessary isolation during program and erase operations through the first layer's deep well structure.
Solution Approach 2:
The patent accepts that the first layer's deep well structure provides the necessary isolation function, while the second layer can use a simpler, cheaper single-well configuration. The second layer's simplified structure acts as a cost-effective solution that doesn't require the expensive deep well formation process, yet still fulfills its functional requirements.
3Reliability
If deep wells are formed in the memory cell region of each layer, then peripheral region isolation is achieved, but device density in the vertical direction is limited
Solution Approach 1:
By segmenting the well formation requirement between layers, the patent enables higher vertical density. The first layer contains the deep wells for isolation, while the second layer can be formed more compactly without deep wells, allowing tighter vertical stacking and increased device density while maintaining necessary isolation functionality.
Solution Approach 2:
The patent transitions from a uniform well configuration across all layers to a differentiated configuration where only the first layer has deep wells. This dimensional differentiation in the vertical direction allows optimization of each layer's structure, enabling higher overall device density while maintaining isolation reliability through the first layer's deep well structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for higher-density, more efficient, and cost-effective production of semiconductor devices with improved reliability by eliminating the need for complex well configurations, enabling higher-speed and lower-power operation.
Implementation Method 1
the first well comprising a semiconducting material doped with impurity of a second type opposite the first type, and the second well comprising a semiconducting material doped with impurity of the first type
Implementation Method 2
the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of the first type and second type
Data Source
AI summary
In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs.