Single-Wire Bus Circuit Scan Testing Without Extra External Pins
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Solution Overview
Problem
Traditional testing methods for complex logic devices in mobile communication devices require multiple physical pins for Scan tests, which increases complexity and footprint, and do not effectively exercise all possible modes of operation.
Innovation Solution
A single-wire bus circuit design that utilizes internal pins to simulate the required Scan test pins, allowing the test to be performed without adding external pins, by using a driver circuit to bridge internal pins for input and output values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional Scan test methods are used with multiple physical pins, then comprehensive testing of all logic device operations is achieved, but device complexity and footprint increase
Solution Approach 1:
The patent combines multiple Scan test functions (SI, SE, CLK, SO) into a single physical pin interface. The test driver circuit multiplexes these functions through time-division or functional multiplexing, allowing one pin to serve multiple purposes that traditionally required separate pins, thereby reducing device complexity while maintaining comprehensive testing coverage
Solution Approach 2:
The single pin interface is designed to perform multiple functions: it can serve as Scan input, Scan enable, clock, and Scan output at different times or under different control conditions. This multi-functional design eliminates the need for dedicated pins for each function, reducing the overall pin count while preserving full Scan test capability
2Adaptability or versatility
If additional external pins are added to single-wire bus circuit for Scan test, then Scan test functionality is enabled, but circuit footprint and complexity increase
Solution Approach 1:
The patent merges the Scan test interface with the existing single-wire bus structure by utilizing internal pins that are already present in the circuit. Rather than adding external pins, the solution combines Scan test functionality with the existing single-pin interface architecture, maintaining compact footprint while enabling comprehensive testing
Solution Approach 2:
The test driver circuit acts as an intermediary that bridges the single external pin interface with the internal Scan test infrastructure. It translates and routes signals appropriately, enabling Scan test functionality through the existing single-wire interface without requiring additional external pins or increasing circuit footprint
Data Source
Figure 1
Figure 2A
Figure 2B~2C
AI summary
A Scan test in a single-wire bus circuit is described in the present disclosure. The single-wire bus circuit has only one external pin for connecting to a single-wire bus. Given that multiple physical pins are required to carry out the Scan test, the single-wire bus circuit must provide additional pins required by the Scan test. In embodiments disclosed herein, the single-wire bus circuit includes a communication circuit under test, and a driver circuit coupled to the communication circuit via multiple internal pins. The driver circuit uses a subset of the internal pins as input pins and another subset of the internal pins as output pins to carry out the Scan test in the communication circuit. As a result, it is possible to perform the Scan test without adding additional external pins to the single-wire bus circuit, thus helping to reduce complexity and footprint of the single-wire bus circuit.