Single Workfunction Metal for Stacked Self-Aligned Transistors
Solution Overview
Problem
The existing technologies for stacked self-aligned transistors require complex deposition and etch processes, which increase the likelihood of degradation of upper gate dielectric and channel materials, and necessitate different workfunction metals for N-channel and P-channel MOS transistors, complicating the fabrication process.
Innovation Solution
Implementing a semiconductor structure with stacked self-aligned transistors using a single workfunction metal that is common to both N-channel and P-channel MOS devices, eliminating the need for dual gate metals and simplifying the fabrication process by using a mid-gap workfunction metal that surrounds both types of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual metal gate is used for stacked self-aligned transistors, then N-channel and P-channel MOS transistors can be fabricated with optimized band offset, but the fabrication process complexity increases and the likelihood of material degradation increases
Solution Approach 1:
The patent merges the previously separate metal gate deposition processes for NMOS and PMOS transistors into a single unified process. A single metal layer is deposited to form gates for both transistor types, eliminating the need for sequential dual metal gate fabrication and reducing process complexity while maintaining device performance
Solution Approach 2:
The patent employs a universal metal gate material that serves both NMOS and PMOS transistors simultaneously. This single metal layer performs the function of both previously separate gates, providing the necessary work function characteristics for both transistor types through a unified fabrication approach
2Ease of manufacture
If complex deposition and etch processes are used for stacked transistors, then dual metal gate can be formed, but the risk of degradation of upper gate dielectric and channel materials increases
Solution Approach 1:
The patent extracts and eliminates the complex etch process step from the fabrication sequence. By using a single metal gate material, the need to selectively etch different metals to expose upper gate dielectric is removed, thereby preventing etch-induced damage to sensitive materials
Solution Approach 2:
The patent performs preliminary material selection by choosing a single metal gate material that can be processed without requiring subsequent selective etching steps. This preliminary decision prevents the need for aggressive etch processes that could damage the upper gate dielectric and channel materials
Data Source
AI summary
Embodiments include transistor devices and a method of forming the transistor devices. A transistor device includes a first conductive layer over a substrate, a first transistor having first interconnects in the first conductive layer, and a second conductive layer on an insulating layer that is on the first conductive layer. The transistor device also includes a second transistor having second interconnects in the second conductive layer, and a gate electrode over the substrate, where the gate electrode has a workfunction metal that surrounds the first and second interconnects. The first and second conductive layers may include conductive materials such as an epitaxial (EPI) layer, a metal layer, or a doped-semiconductor layer. The transistor device may further include a dielectric surrounding the interconnects as the dielectric is surrounded with the workfunction metal, and a transition layer disposed between the dielectric and interconnects. The dielectric may include a high-k dielectric material.