Singulated Die Testing with Multi-Level Carrier
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Solution Overview
Problem
Current semiconductor die testing methods are limited by the need to test wafers as a whole, which restricts temperature range, introduces defects during thinning, and limits parallel testing due to probe card limitations and packing constraints, leading to inefficiencies and increased costs when identifying faulty die.
Innovation Solution
A method and apparatus for testing singulated semiconductor die using a multi-level die carrier with independently movable die sub-carriers and electrical contactors, allowing for precise registration and alignment, and enabling testing at higher temperatures and in parallel, with improved signal quality and reduced waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-level testing is performed using probe cards, then testing can be conducted on multiple die simultaneously, but the testing is restricted to limited temperature ranges and introduces defects during thinning
Solution Approach 1:
The patent segments the wafer into individual singulated die and tests them separately rather than testing the entire wafer at once. This allows each die to be tested independently at optimal temperatures without the constraints of wafer-level testing, eliminating thermal restrictions and thinning defects while maintaining parallel testing capability through batch processing of multiple singulated die
Solution Approach 2:
The patent performs preliminary actions by singulating the die before testing, allowing temperature conditioning and alignment to be completed in advance. This preliminary singulation and alignment process enables subsequent testing to proceed without the harmful effects of wafer thinning during the actual test, while still allowing for efficient batch processing
2Measurement precision
If probe cards with fixed probe arrays are used, then alignment can be achieved through mechanical movement, but parallel testing is limited due to probe card constraints and packing density
Solution Approach 1:
The patent transitions from static probe card arrays to dynamic, independently movable die carriers with adjustable positioning. Each die carrier can be individually positioned and aligned, allowing for precise measurement accuracy while significantly increasing parallel testing capacity by accommodating multiple die carriers simultaneously in the testing apparatus
Solution Approach 2:
The patent adds dimensional flexibility by allowing die carriers to move independently in multiple degrees of freedom rather than relying solely on planar probe card arrays. This vertical and lateral adjustability of individual die carriers enables both high precision alignment and increased parallelism by stacking and arranging multiple carriers in three-dimensional space
3Ease of operation
If wafers are thinned for testing, then access to die is improved, but defects are introduced during the thinning process
Solution Approach 1:
The patent performs the singulation action preliminarily, before testing, by separating die from the wafer substrate in advance. This preliminary separation provides adequate access to die electrical contacts for testing without requiring subsequent thinning operations, thereby maintaining die integrity while achieving the necessary accessibility for probe contact
Solution Approach 2:
The patent extracts individual die from the wafer substrate through singulation, removing them for separate testing. This extraction process provides full access to die surfaces and contacts without the need for thinning, as the die are tested in their singulated state before packaging, eliminating the harmful thinning step entirely
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient identification of faulty die before packaging, reduces waste, and improves testing quality by allowing higher temperature testing and parallel testing of singulated die, thereby reducing costs and increasing the reliability of semiconductor products.
Implementation Method 1
causing movement in an elastomeric element positioned between one of the die sub-carriers and the die carrier
Implementation Method 2
causing movement of a spring that attaches one of the die sub-carriers to the die carrier
Data Source
AI summary
In one embodiment, a method for testing a plurality of singulated semiconductor die involves 1) placing each of the singulated semiconductor die on a surface of a die carrier, 2) mating an array of electrical contactors with the plurality of singulated semiconductor die, and then 3) performing electrical tests on the plurality of singulated semiconductor die, via the array of electrical contactors.