Dual Shielding Structure for SiP Electromagnetic Interference

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Solution Overview

Problem

The integration of multiple semiconductor dice in System-in-Package (SiP) devices leads to electromagnetic interference (EMI) that degrades circuit performance, necessitating a solution to reduce such interference.

Innovation Solution

A semiconductor device design incorporating an internal shielding layer with a projection overlapping the electronic components, exposed laterally, and an external shielding layer covering the encapsulants, both made of conductive materials like Al, Cu, or carbonyl iron, to shield against EMI.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple semiconductor dice are integrated in System-in-Package (SiP) devices, then functionality and performance are improved, but electromagnetic interference (EMI) increases and degrades circuit performance

Engineering Contradiction:
ImprovefunctionalityVSAvoidelectromagnetic interference
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The shielding structure is divided into two distinct segments: an internal shielding layer positioned within the package to shield specific sensitive components, and an external shielding layer positioned outside the package to shield against external EMI sources. This segmentation allows targeted protection while maintaining the functional integration of multiple semiconductor dice.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The internal shielding layer is nested within the package structure, and the external shielding layer is nested over the package, creating a nested shielding configuration. The internal shielding layer has exposed lateral surfaces that contact the external shielding layer, forming a continuous nested protective structure that reduces EMI while preserving device functionality.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Object-affected harmful factors

If shielding layers are added to reduce EMI, then electromagnetic interference is reduced, but device complexity increases

Engineering Contradiction:
Improveelectromagnetic interferenceVSAvoiddevice complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The dual-layer shielding structure serves multiple functions: the internal shielding layer protects specific sensitive components from internal EMI sources, the external shielding layer protects against external EMI sources, and the exposed lateral surfaces of the internal shielding layer provide electrical contact with the external shielding layer to create a continuous shield. This multi-functional design reduces EMI effectively while managing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The combination of internal and external shielding layers effectively reduces electromagnetic interference, enhancing the performance and functionality of SiP devices by minimizing interference-induced degradation.

Implementation Method 1

an internal shielding layer disposed between the bottom encapsulant and the top encapsulant... and an external shielding layer covering the bottom encapsulant and the top encapsulant

Methodology Applied
Scientific EffectElectromagnetic shielding: Faraday Cage

Data Source

PatentUS12575421B2Semiconductor device comprising different shielding layers to provide reduced electromagnetic interference and method for making the same
Publication Date: 2026.03.10 STATS CHIPPAC LTD
  • US12575421B2 patent drawing
  • US12575421B2 patent drawing
  • US12575421B2 patent drawing

AI summary

A semiconductor device and a method for making the same are provided. The semiconductor device includes: a substrate including a substrate top surface and a substrate bottom surface; an electronic component mounted on the substrate top surface; a bottom encapsulant disposed on the substrate top surface and encapsulating the electronic component; a top encapsulant disposed on the bottom encapsulant; an internal shielding layer disposed between the bottom encapsulant and the top encapsulant, wherein a projection of the internal shielding layer onto the substrate top surface overlaps with the electronic component, the internal shielding layer has an internal shielding layer lateral surface, and a portion of the internal shielding layer lateral surface is exposed from the bottom encapsulant and the top encapsulant; and an external shielding layer covering the bottom encapsulant and the top encapsulant and contacting with the exposed portion of the internal shielding layer lateral surface.