Silicon Photonic IC Stack Verification Using Dummy LVS Layers
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Solution Overview
Problem
In semiconductor manufacturing, aligning contact pads between stacked circuits is challenging, leading to increased risks of open or short circuits, especially when silicon photonic devices are involved, making it difficult to verify connection and routing quality and stacking quality of integrated circuit stacks.
Innovation Solution
The introduction of dummy layers, such as SIPH_LVS and 3D_STACKING_LVS, added to terminals of silicon photonic devices and contact pads, allows for verification through layout versus schematic checks, ensuring correct electrical connections and stacking quality by comparing layout representations with schematic diagrams using tools like Calibre or Quartz LVS.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact pads are used to electrically connect stacked circuits, then electrical connections between stacked circuits are established, but misalignment between contact pads increases the risk of open circuits or short circuits
Solution Approach 1:
The patent applies preliminary action by adding dummy layers to contact pads and SiPH device terminals during the layout design phase, before actual manufacturing. These dummy layers serve as verification markers that enable pre-manufacturing checks of contact pad alignment and routing connections through layout versus schematic comparisons, allowing potential misalignments to be detected and corrected before the costly stacking process
Solution Approach 2:
The patent uses dummy layers as intermediary elements that facilitate verification without interfering with the actual electrical connections. These dummy layers act as mediators between the physical contact pad structure and the verification process, enabling designers to check alignment and routing quality through LVS tools without adding physical test structures that would complicate the stacking process or require additional manufacturing steps
2Adaptability or versatility
If silicon photonic devices are included in stacked circuits, then functional integration is enhanced, but verification of connection and routing quality becomes more challenging
Solution Approach 1:
The patent applies preliminary action by incorporating dummy layers into the layout design of SiPH devices during the planning phase. These dummy layers are added to device terminals and contact pads before manufacturing, enabling verification of routing connections and alignment through automated LVS tools. This approach allows complex SiPH device integrations to be verified systematically without requiring complex post-manufacturing test structures or measurement procedures
Solution Approach 2:
The patent uses dummy layers as simplified copies or representations of the actual SiPH device terminals and contact pads. These dummy layers replicate the geometric and positional characteristics of the real structures, allowing verification tools to check routing and alignment without needing to interact with the actual complex SiPH devices. This copying approach simplifies the verification process while maintaining accuracy for complex photonic integrations
3Measurement precision
If manual verification methods are used to check stacking quality, then detailed inspection is possible, but verification time and complexity increase significantly
Solution Approach 1:
The patent creates simplified copies of the physical stacking structure in the form of dummy layers within the layout database. These dummy layer representations capture the essential geometric and positional information of contact pads and device terminals, allowing automated LVS tools to perform verification operations rapidly without needing to physically inspect or measure the actual stacked devices. This copying approach maintains verification accuracy while dramatically reducing the time required compared to manual inspection methods
Solution Approach 2:
The patent replaces manual mechanical verification processes with automated computer-based LVS tools. Instead of requiring physical measurement and manual comparison of stacked circuits, the dummy layers enable automated electronic verification through software that compares layout representations against schematic designs. This substitution of mechanical manual processes with automated electronic systems maintains high verification accuracy while significantly reducing verification time and human labor requirements
Data Source
AI summary
A method and a system for verifying an integrated circuit stack having a silicon photonic (SIPH) device is introduced. A single first dummy layer is added to at least one terminal of the SIPH device in a first layout of the first integrated circuit, wherein a shape of the single first dummy layer added to the at least one terminal of the SIPH device maps a shape of the at least one terminal of the SIPH device. A first layout versus schematic (LVS) check is performed on the first integrated circuit based on the single first dummy layer added to the at least one terminal of the SIPH device to verify a connection of the SIPH device in the first integrated circuit.