SIT Semiconductor Device With PN Super-Junction Gate
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Solution Overview
Problem
Conventional semiconductor devices, such as static induction transistors (SIT), face challenges in achieving a balance between low specific resistance (Rsp) and capacitance, particularly in high-frequency applications, where planar gate SITs have high Rsp and recessed gate SITs are limited by parasitic capacitance.
Innovation Solution
The integration of a trench formation with a gate sandwiched between thick dielectric layers and connected to a region of a PN super-junction structure, allowing for control of the current path, which reduces both specific resistance and capacitance by utilizing a concentration gradient in the epitaxial layer and angled implantation for charge balancing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional SIT device structures are used, then manufacturing is simplified, but the balance between specific resistance and capacitance cannot be achieved for high-frequency applications
Solution Approach 1:
The patent segments the gate structure into distinct regions: a recessed portion extending into the substrate and an isolated configuration separated from the drain region. This segmentation allows independent optimization of each region's function - the recessed gate controls current flow for low specific resistance, while the isolation structure eliminates parasitic capacitance pathways, achieving the desired performance balance without significantly complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in semiconductor devices with significantly lower Rsp and capacitance compared to conventional SIT devices, enhancing performance in high-frequency applications by reducing parasitic capacitance and improving charge balance.
Implementation Method 1
The reverse bias that can be applied to the gate can expand the depletion region and pinch-off and block the current flow
Implementation Method 2
utilizing a concentration gradient in the epitaxial layer and angled implantation for charge balancing
Data Source
AI summary
Semiconductor devices and methods for making such devices that are especially suited for high-frequency applications are described. The semiconductor devices combine a SIT (or a junction field-effect transistor [JFET]) architecture with a PN super-junction structure. The SIT architecture can be made using a trench formation containing a gate that is sandwiched between thick dielectric layers. While the gate is vertically sandwiched between the two isolating regions in the trench, it is also connected to a region of one conductivity type of the super-junction structure, thereby allowing control of the current path of the semiconductor device. Such semiconductor devices have a lower specific resistance and capacitance relative to conventional planar gate and recessed gate SIT semiconductor devices. Other embodiments are described.