Six-transistor inverter layout for switching power converters
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Solution Overview
Problem
Conventional full-bridge inverter topologies face high switching losses in bipolar PWM modulation and large leakage currents in unipolar PWM modulation, leading to inefficiencies and safety concerns, while also experiencing voltage spikes and reliability issues due to parasitic inductance in switching power converters.
Innovation Solution
A six-transistor topology layout for switching power converters is optimized by arranging power transistor units and capacitors in parallel bridge arms with specific connections and commutation circuits to minimize parasitic inductance, enhancing electrical characteristics and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional full-bridge topology with bipolar PWM modulation is used, then the inverter can convert DC to AC power, but switching losses become huge and efficiency becomes low
Solution Approach 1:
The conventional full-bridge topology is segmented into three separate bridge arms with six independent power transistor units. Each bridge arm operates independently with its own switching devices, allowing for unipolar PWM modulation without the high switching losses of bipolar modulation. This segmentation enables the system to avoid the fundamental switching loss problem of conventional bipolar full-bridge topologies while maintaining full-bridge functionality.
2Loss of energy
If conventional full-bridge topology with unipolar PWM modulation is used, then switching losses are reduced, but leakage currents become large and system safety is affected
Solution Approach 1:
By dividing the bridge into three independent arms with six separate power transistor units, each unit can be controlled independently. This segmentation allows the system to use unipolar PWM modulation while the independent control of each unit prevents the large leakage currents that occur in conventional full-bridge topologies, thus resolving the contradiction between reduced switching losses and leakage current control.
3Power
If switching frequency is increased to achieve thinner and smaller electronic products, then power density is improved, but parasitic inductance causes voltage spikes and reliability decreases
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional spatial arrangement of the six power transistor units on the carrier board. By optimizing the spatial positioning in three dimensions and minimizing the loop areas formed by commutation paths, the parasitic inductance is reduced. This dimensional optimization allows high switching frequencies to be used without excessive voltage spikes, thereby improving power density while maintaining reliability.
4Reliability
If circuit parasitic inductance is reduced to improve electrical characteristics, then voltage spikes are reduced and reliability is improved, but device complexity increases due to optimized layout requirements
Solution Approach 1:
The patent applies local quality optimization by specifically arranging the six power transistor units in particular positions on the carrier board to minimize commutation loop areas. Instead of uniformly distributing components, each power transistor unit is placed in an optimized location that locally minimizes parasitic inductance for its specific commutation paths. This localized optimization achieves reduced parasitic inductance and improved reliability without requiring complete redesign of the entire system architecture.
Data Source
AI summary
A layout of a switching power converter, wherein the switching power converter includes: a capacitor unit receiving or outputting DC voltage; six power transistor units transforming the DC voltage to the AC voltage or the AC voltage to the DC voltage; and a carrier board with the capacitor unit and the six power transistor units on. The layout of the switching power converter includes a first commutation loop and a second commutation loop, in which the six power transistor units are arranged on the same surface of the carrier board. In order to ensure the first commutation loop and the second commutation loop as short as possible, the fifth power transistor unit is located at a middle position of the carrier board, surrounded by the other five power transistor units as closely as possible.