Skew-CDR Timing Phase Adjustment for Data Eye Symmetry
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Solution Overview
Problem
In high-data-rate communication systems, frequency-dependent signal loss and dispersion in communication channels lead to signal degradation, making it challenging for CDR circuits to maintain low bit-error-ratios and achieve symmetric data eyes, especially when channel characteristics are unknown and vary over time.
Innovation Solution
A Skew-CDR circuit that adaptively adjusts the sampling phase of timing error latches relative to data sampling latches, forming a symmetric data eye by skewing the phase of the timing error clock, thereby optimizing cursor and precursor amplitudes and improving eye margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional baud-rate CDR circuits sample at the baud rate without oversampling, then device complexity is reduced, but the ability to achieve symmetric data eyes and maintain low bit-error-ratios deteriorates under frequency-dependent signal loss and dispersion
Solution Approach 1:
The patent divides the sampling process into multiple phases within each baud period, using separate data sampling latches and timing error latches. This segmentation allows independent optimization of data sampling and timing error detection, enabling symmetric data eyes without requiring full oversampling of the data path, thus maintaining low complexity while improving reliability
Solution Approach 2:
The patent introduces a phase dimension by implementing multiple sampling phases (data sampling phase and timing error sampling phase) within the time domain. By skewing the timing error clock phase relative to the data clock phase, the system creates an additional degree of freedom to achieve symmetric data eyes and reduce bit-error-ratios without increasing overall sampling rate or device complexity
2Device complexity
If the sampling phase is fixed in conventional baud-rate CDR circuits, then device complexity is reduced, but adaptability to unknown and time-varying channel characteristics deteriorates
Solution Approach 1:
The patent implements dynamic phase adjustment by introducing a skew factor that can be adaptively modified based on detected timing errors and channel conditions. The timing error clock phase is skewed by a variable amount relative to the data clock phase, allowing the system to adapt to unknown and time-varying channel characteristics while maintaining a relatively simple circuit structure
Solution Approach 2:
The patent employs feedback mechanisms where timing error samples obtained at the skewed phase are used to adjust the skew factor and optimize the sampling phase. This feedback loop enables automatic adaptation to channel variations without requiring complex predetermined channel characterization, improving versatility while keeping device complexity manageable
3Device complexity
If timing error latches sample at the same phase as data sampling latches, then device complexity is reduced, but data eye symmetry and horizontal eye margin deteriorate under signal degradation
Solution Approach 1:
The patent deliberately introduces asymmetry in the sampling phases by skewing the timing error clock phase relative to the data clock phase. This asymmetric phase relationship allows the timing error detection to occur at an optimal point that compensates for channel-induced distortions, achieving symmetric data eyes at the data sampling point while maintaining relatively simple circuit implementation
Data Source
AI summary
In described embodiments, a transceiver includes a baud-rate clock and data recovery (CDR) module with an eye sampler, and an adaptation module for adaptively setting parameters of various circuit elements, such as timing, equalizer and gain elements. Data sampling clock phase of the CDR module is set for sampling at, for example, near the center of a data eye detected by the eye sampler, and the phase of data error sampling latch(es) is skewed by the CDR module with respect to the phase of the data sampling latch. Since the error signal driving the timing adaptation contains the information of the pulse response that the CDR module encounters, the phase of timing error sampling latch(es) of the CDR module is skewed based on maintaining a relative equivalence of input pulse response residual pre-cursor and residual post-cursor with respect to the timing error sampling clock phase.