Skip Via Inner Spacer Layout for Shorting and TDDB Control
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Solution Overview
Problem
The challenge in integrated circuits is the increased risk of shorting and time-dependent dielectric breakdown in skip vias due to their deep depths and the potential for via-to-line shorting, which complicates scaling and performance as device dimensions decrease.
Innovation Solution
The introduction of an inner spacer only on skip via structures to prevent shorting and improve dielectric breakdown, while maintaining contact resistance and critical dimension targets, using dielectric materials like silicon oxide or nitride for the spacer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If skip vias are used to connect upper metal lines to lower metal lines through multiple interlevel dielectric levels, then the number of interconnect layers is reduced and routing complexity is decreased, but the risk of shorting to intermediate metal lines increases and time-dependent dielectric breakdown becomes more likely
Solution Approach 1:
The patent introduces a spacer structure as an intermediary element between the skip via and intermediate metal lines. This spacer acts as a protective barrier that prevents direct contact between the via and metal lines, thereby eliminating the shorting risk while maintaining the routing simplification benefits of skip vias.
Solution Approach 2:
The spacer is formed on the sidewalls of the skip via opening before the via is filled with conductive material. This preliminary protective structure prevents potential shorting before it can occur, addressing the reliability concern in advance while allowing the skip via structure to be implemented.
2Reliability
If an inner spacer is added to skip via structures to prevent shorting, then reliability is improved, but manufacturing complexity and process steps increase
Solution Approach 1:
The patent combines the spacer formation with the existing via opening formation process. The spacer is deposited conformally on the sidewalls during the same process sequence as the via opening creation, merging two functions into one integrated process flow rather than adding separate discrete steps.
Solution Approach 2:
The spacer structure serves multiple functions simultaneously: it prevents shorting to intermediate metal lines, provides mechanical support during subsequent processing steps, and defines the via opening boundaries. This multi-functionality reduces the need for additional specialized structures or processes.
3Reliability
If the spacer material is deposited conformally on skip via sidewalls, then shorting prevention is achieved, but the critical dimension control and contact resistance may be affected
Solution Approach 1:
The patent carefully controls the deposition parameters of the spacer material, including thickness, composition, and deposition conditions. By adjusting these parameters, the spacer provides adequate protection against shorting while maintaining appropriate dimensions that do not interfere with via filling or electrical contact properties.
Solution Approach 2:
The spacer is applied selectively only on the sidewalls of skip via openings, not on all structures. This localized application ensures that the protective function is provided where needed (at the via-metal line interface) without unnecessarily affecting other areas or introducing additional complexity elsewhere in the structure.
Data Source
AI summary
A microelectronics structure including a skip level via extending from an upper level metal line in an upper level of the at least two interlevel dielectric levels through a first an interlevel dielectric level that is on the substrate level without contacting an interlevel metal line. The skip level via extends into electrical contact with a first element of electrical contact features in a lower level of the at least two interlevel dielectric levels. The skip level via includes a spacer that is present on sidewalls of the skip level via. The structure also includes a single level via, in which the dielectric material of the spacer of the skip level via is not present on the sidewalls of the single level via.