Slack Time Recycling in Logic Pipeline Verification
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Solution Overview
Problem
Existing electronic design verification systems face challenges in reducing system speed due to signal propagation and translation delays, which necessitate lowering the system clock frequency, thereby increasing compilation and synthesis times.
Innovation Solution
A computing system implements a verification configuration tool that identifies stages in a logic pipeline spanning across partitions in a verification system, alters timing to reduce slack in adjacent stages, and recycles this slack to increase clock frequency or propagate delay time, thereby optimizing the logic pipeline configuration for configurable hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware-based features are used to implement logic design in emulation and prototyping systems, then functionality and realism are improved, but signal propagation delays and translation delays increase, causing system speed to decrease
Solution Approach 1:
The patent recovers slack time created by hardware-based features (which cause delays) and reuses it to increase clock frequency. The harmful delays are converted into beneficial slack time that can be allocated to other critical paths, allowing the system to run faster overall while maintaining functional accuracy.
Solution Approach 2:
The patent dynamically adjusts timing parameters by recovering slack from non-critical paths and applying it to critical paths. This allows the clock frequency to be increased while still meeting all timing constraints, effectively changing the timing parameters of the system to optimize performance.
2Measurement precision
If hardware-based features are used to implement logic design, then signal translation accuracy is improved, but compilation time and synthesis time increase due to added complexity
Solution Approach 1:
The patent converts the complexity introduced by hardware-based features into recoverable slack time. By automatically analyzing and recovering this slack, the system offsets the compilation overhead and enables faster clock frequencies, turning the initial complexity burden into a performance advantage.
3Reliability
If clock frequency is reduced to accommodate worst case delay, then timing constraints are met, but throughput of functional verification decreases
Solution Approach 1:
The patent changes the timing parameters by recovering slack from non-critical paths and applying it to critical paths. This allows the clock frequency to be increased beyond what would be required if the worst-case delay alone determined the frequency, thereby maintaining timing constraint satisfaction while improving verification throughput.
Solution Approach 2:
The patent converts the conservative timing approach (which limits clock frequency) into an opportunity for optimization. By recovering and redistributing slack time, the system can run at higher frequencies while still meeting all timing constraints, thereby improving productivity without sacrificing reliability.
Data Source
AI summary
This application discloses a computing system to identify a stage of a logic pipeline described in a circuit design that, when implemented in configurable hardware, spans between partitions in the configurable hardware. The computing system can modify the circuit design to alter a timing for logic operations in the logic pipeline, which reduces slack in at least one stage in the logic pipeline adjacent to the identified stage in the logic pipeline. The computing system can utilize the slack reduced from at least one of the stages adjacent to the identified stage to increase a clock frequency in the configurable hardware or increase a time available for propagation delay associated with the identified stage. The computing system can generate a configuration for the configurable hardware that implements the logic pipeline with the altered timing in the configurable hardware.