Slave Latch Retention Flop for Low-Leakage Standby Data Hold
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Solution Overview
Problem
Existing data retention circuits in portable devices face challenges in achieving reduced leakage current while maintaining desirable performance and silicon area, often requiring trade-offs that compromise one parameter for improvement in another, and may become less robust at lower voltages.
Innovation Solution
A data retention apparatus and method that uses a first latch to store data and a second latch to retain it in standby power mode, with a switching circuit and a standby power source to minimize leakage current, excluding clock path gating and optimizing performance and silicon area by reducing active devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If data retention circuits use traditional flip-flop designs with always-on power supply, then data retention functionality is maintained, but leakage current increases during standby power mode
Solution Approach 1:
The flip-flop is divided into two separate latches: a master latch that is powered down during standby mode, and a slave latch that remains powered to retain data. This segmentation allows the circuit to reduce leakage current by powering off the master latch while maintaining data retention capability through the slave latch, resolving the contradiction between energy loss and reliability
Solution Approach 2:
Data is pre-transferred from the master latch to the slave latch before the master latch is powered down. The slave latch is prepared in advance to assume the data retention function, ensuring that data is already secured in the powered portion of the circuit before power is removed from the master latch, thus maintaining reliability while reducing leakage
2Loss of energy
If data retention circuits use additional active devices for reduced leakage, then leakage current decreases, but silicon area increases
Solution Approach 1:
The slave latch serves multiple functions: it acts as part of the normal flip-flop operation during active mode and simultaneously serves as the data retention element during standby mode. This multi-functionality eliminates the need for separate dedicated retention circuitry, reducing silicon area while maintaining the ability to reduce leakage current through selective power management
Solution Approach 2:
The data retention functionality is merged into the existing slave latch structure of the flip-flop rather than being implemented as a separate circuit. By combining the retention function with the existing latch that is already part of the flip-flop architecture, the solution reduces silicon area while still achieving leakage reduction through selective power management
3Speed
If data retention circuits optimize for performance, then speed improves, but leakage current increases
Solution Approach 1:
The circuit dynamically adjusts its power consumption based on operational mode. During active mode, both latches are powered to enable fast data transfer and maintain performance. During standby mode, the master latch is powered down to reduce leakage current while the slave latch maintains data retention. This dynamic power management resolves the contradiction by allowing performance optimization when needed and leakage reduction when performance requirements are lower
Data Source
AI summary
In a method and apparatus for data retention, a first latch latches a data input and a second latch that is coupled to the first latch retains the data input while the first latch is inoperative in a standby power mode. The second latch includes a second latch inverter having an inverter input and an inverter output. A switching circuit, which may be implemented as a tristate inverter, is coupled to the inverter output, the inverter input, and a retention signal. The switching circuit is operable in the standby power mode to assert a logic state at the inverter input responsive to the retention signal. The logic state is in accordance with the data input retained in the standby power mode. A standby power source is operable to provide power in the standby power mode to the second latch inverter, the switching circuit and the retention input.