Single-Level Cell Memory Programming With Concurrent Sub-Blocks
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Solution Overview
Problem
Existing memory devices face performance delays due to sequential programming operations for each page in single-level cell (SLC) memory, which include hardware initialization, seed operation, program verify, and final verification, causing unwanted delays.
Innovation Solution
Implement a local media controller to program multiple pages concurrently to a set of sub-blocks in SLC memory, performing a reduced seed operation before programming each sub-block and a single program verify operation after all sub-blocks are programmed, eliminating intermediate verify operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential programming operations are performed for each page in SLC memory, then programming reliability is maintained through program verify operations, but programming time increases significantly
Solution Approach 1:
The patent combines multiple sequential programming operations into a single concurrent operation. Multiple pages are programmed simultaneously to different sub-blocks in parallel, and multiple program verify operations are merged into a single concurrent verify operation that checks all sub-blocks at once. This reduces the total number of sequential steps while maintaining reliability through comprehensive verification.
Solution Approach 2:
The patent divides the SLC memory array into multiple sub-blocks that can be programmed independently and concurrently. Each sub-block can receive different pages of data simultaneously, allowing parallel programming operations. This segmentation enables multiple pages to be programmed in parallel without interfering with each other, significantly reducing programming time while maintaining verify operations for each sub-block.
2Measurement precision
If intermediate program verify operations are performed after each sub-block programming, then programming accuracy is ensured, but system performance decreases due to sequential delays
Solution Approach 1:
The patent merges multiple intermediate program verify operations into a single concurrent program verify operation that performs verification on all sub-blocks simultaneously. This maintains programming accuracy by verifying all programmed pages while eliminating the sequential delays between individual verify operations, thereby improving system performance.
Solution Approach 2:
The patent implements continuous useful action by performing program verify operations concurrently with the programming operations. The verify operation is executed as a single continuous process that checks all sub-blocks in parallel, rather than sequentially verifying each sub-block after programming. This maintains accuracy while keeping the system productive through parallel verification.
Data Source
AI summary
A memory device comprising an array of memory cells configured as single-level cell memory. Control logic is operatively coupled to the array and is to cause a seed operation to be performed on sub-blocks of the array to precondition voltage levels of the sub-blocks for programming. The control logic causes pages of data to be programmed to respective ones of the sub-blocks. The control logic causes a program verify to be performed on memory cells of the sub-blocks after programming the pages of data. The control logic causes a check verification operation be performed at the sub-blocks to determine results of the program verify and that the pages of data have been completely programmed. The control logic exits a program operation of the sub-blocks in response to passing the check verification operation.