SLC Program-Verify With Recovery-Latch Data Buffering
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Solution Overview
Problem
Existing memory devices face inefficiencies in SLC programming due to the loss of data during inhibit operations, requiring additional latches for multi-page programming, which increases costs and reduces data recoverability.
Innovation Solution
Implementing a ganged SLC verify operation followed by selective serial program verify operations, with temporary data buffering in a recovery latch to ensure data recoverability without additional latches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional latches are added for multi-page programming, then data recoverability is improved, but device complexity and cost increase
Solution Approach 1:
The patent introduces a recovery latch as an intermediary component that temporarily stores data during the program-verify operation. This single recovery latch acts as a mediator between the source latch and the memory array, enabling data recovery without requiring multiple latches for multi-page programming. The recovery latch preserves data integrity during inhibit operations while maintaining system simplicity.
2Manufacturing precision
If inhibit operation is performed during programming, then programming precision is improved, but data is lost during the operation
Solution Approach 1:
The patent performs preliminary data backup by copying data from the source latch to the recovery latch before executing the inhibit operation. This preliminary action ensures that data is preserved in the recovery latch before the inhibit operation removes data from the source latch, preventing data loss while maintaining programming precision through the inhibit operation.
Solution Approach 2:
The recovery latch serves as a cushioning mechanism that protects data from being lost during inhibit operations. By having data replicated in the recovery latch beforehand, the system creates a safety buffer that prevents information loss when the source latch data is removed during programming operations.
3Speed
If single program pulse is applied for SLC programming, then programming speed is improved, but verify operation complexity increases
Solution Approach 1:
The patent segments the verify operation into two distinct phases: a concurrent ganged SLC verify operation that checks multiple cells simultaneously using a single program verify pulse, and selective serial program verify operations for individual cells. This segmentation allows the system to maintain high programming speed through parallel verification while managing complexity by handling verification in organized stages rather than a single complex operation.
Data Source
AI summary
A memory device includes a memory array configured as single-level cell (SLC) memory, a page buffer including a source latch and data recovery latch, and control logic. The control logic causes a program verify voltage to be applied to a selected wordline during a ganged SLC verify operation to be performed concurrently on a set of memory cells that have been programmed. The control logic, in response to the set of memory cells failing to pass the ganged SLC verify operation, buffers first data, which is associated with a first memory cell, in the data recovery latch, causes a program verify operation to be performed on the first memory cell and, in response to detecting a pass of the program verify operation on the first memory cell, moves the first data in the data recovery latch back into the source latch.