Slew Rate Control Circuit for Stable Duty Cycle and Lower EMI
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Solution Overview
Problem
Conventional DRAM output data buffer circuits face performance disturbances when controlling slew rate, as they fail to adjust slew rate without affecting signal duty cycle, leading to electromagnetic interference (EMI) issues.
Innovation Solution
A slew rate control circuit comprising a slew rate control unit, capacitive delay unit, delay unit, and output units, which utilize control signals and capacitors to adjust the slew rate while maintaining signal duty cycle, employing a combination of inverters, NOR and NAND gates, and capacitors to control voltage rates and delay waveforms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the slew rate is increased to improve data transmission speed, then the charging speed of the capacitor is increased, but electromagnetic interference (EMI) effect is generated
Solution Approach 1:
The patent applies dynamics by making the slew rate adjustable rather than fixed. The circuit can dynamically change the slew rate based on different operating modes (first mode with faster slew rate for high-speed transmission, second mode with slower slew rate for low EMI), allowing the system to adapt between speed and EMI reduction requirements
Solution Approach 2:
The patent changes the slew rate parameter to resolve the contradiction. By controlling the slew rate to have different values in different modes (faster in first mode, slower in second mode), the system can achieve both high-speed transmission and EMI reduction as needed, directly addressing the trade-off between transmission speed and electromagnetic interference
2Adaptability or versatility
If the slew rate is controlled by conventional DRAM output data buffer circuit, then the slew rate can be adjusted, but performance disturbance effect is introduced
Solution Approach 1:
The patent segments the output buffer circuit into multiple independent output units (first output unit, second output unit, third output unit), each capable of independent operation with controlled slew rates. This segmentation allows the circuit to maintain stable performance by distributing the control function across multiple units rather than relying on a single conventional buffer circuit that introduces performance disturbance
3Object-generated harmful factors
If the slew rate is adjusted to reduce EMI, then the maximum rate of variation of output voltage is decreased, but data transmission speed is reduced
Solution Approach 1:
The circuit dynamically adjusts the slew rate based on operational requirements. When EMI reduction is prioritized, the circuit operates in the second mode with slower slew rate. When transmission speed is prioritized, it switches to the first mode with faster slew rate, making the system adaptable to different operational contexts
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit effectively adjusts slew rate in various modes without introducing performance disturbances, maintaining signal duty cycle stability and reducing EMI, thereby enhancing data output performance.
Implementation Method 1
The capacitive delay unit is coupled to the slew rate control unit and configured to receive an input signal
Implementation Method 2
The delay unit is coupled to the capacitive delay unit
Data Source
AI summary
The slew rate control circuit includes a slew rate control unit, a capacitive delay unit, a delay unit, a first output unit, a second output unit, and a third output unit. The slew rate control unit is used for receiving a plurality of control voltages. The capacitive delay unit is coupled to the slew rate control unit for receiving an input signal. The delay unit is coupled to the capacitive delay unit. The first output unit and the second output unit are coupled to the capacitive delay unit. The third output unit is coupled to the delay unit. The first output signal and the second output signal are two signals without controllable slew rates. A slew rate of the third output signal is controlled by the capacitive delay unit. A slew rate of the fourth output signal is controlled by the capacitive delay unit and the delay unit.