Sliced Chip Carrier Panels From Encapsulated Wiring Block
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Solution Overview
Problem
Existing chip carriers are relatively expensive to produce, necessitating the development of more cost-effective alternatives for semiconductor packaging applications.
Innovation Solution
A method involving arranging wires in parallel within a wiring fixture, encapsulating them to form a block, and slicing it into discrete panels with conductive vias, which can be used as chip carriers suitable for various packaging applications, leveraging existing semiconductor equipment and processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional chip carrier manufacturing methods are used, then reliable chip carriers are produced, but production cost is high
Solution Approach 1:
The patent divides a single large wiring block into multiple smaller panels through slicing, with each panel serving as an independent chip carrier. This segmentation allows mass production from one block while maintaining reliability through consistent wire geometry and encapsulation, thereby reducing per-unit cost.
Solution Approach 2:
The patent creates multiple identical chip carriers by replicating the wire arrangement and encapsulation pattern across numerous panels derived from a single wiring block. This copying approach ensures consistent electrical performance while achieving economies of scale in production.
2Manufacturing precision
If multiple chip carriers are produced individually, then each carrier meets specifications, but production efficiency is low
Solution Approach 1:
The patent combines multiple chip carrier production processes into a single integrated workflow: wires are arranged once in a fixture, encapsulated as one block, then sliced into multiple panels. This merging of operations maintains precision through consistent wire positioning while dramatically improving productivity by producing many carriers simultaneously.
Solution Approach 2:
The patent performs preliminary wire arrangement and encapsulation in a fixed geometric pattern before slicing. This preliminary action ensures all wires are precisely positioned and encapsulated once, and the subsequent slicing process automatically replicates this precision across all resulting panels, maintaining manufacturing precision while boosting productivity.
3Measurement precision
If wires are arranged manually for each carrier, then precise positioning is achieved, but labor cost and time increase
Solution Approach 1:
The patent transitions from arranging wires individually for each carrier (one-dimensional sequential process) to arranging wires once in a three-dimensional fixture that accommodates multiple future panels. This dimensional change allows precise wire positioning to be achieved once, then replicated across numerous carriers through slicing, dramatically reducing time while maintaining accuracy.
Data Source
AI summary
A method of fabricating chip carriers suitable for use in packaging integrated circuits and other electronic, electro-mechanical and opto-electronic devices is described. In general, a number of wires (or wires and rods) are arranged in parallel in a wiring fixture. After the wires are positioned, they are encapsulated to form an encapsulated wiring block. The wiring block is then sliced to form a number of discrete panels. Preferably, the various wires are geometrically positioned such that each resulting panel has a large number of device areas defined therein. The encapsulant in each panel effectively forms a substrate and the wire segments in each panel form conductive vias that extend through the substrate. The resulting panels/chip carriers can then be used in a wide variety of packaging applications.