SLIMbus Secondary Data Lines for Bandwidth Expansion
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Solution Overview
Problem
The existing SLIMbus communication standard faces challenges in providing sufficient bandwidth and throughput for modern mobile devices, particularly for applications involving audio and video data, as it typically relies on a single data line and clock line, limiting its ability to meet the increasing demands for communication between components.
Innovation Solution
The proposed solution involves configuring additional secondary data lines on the SLIMbus to enhance communication bandwidth, where a configuration message is sent over the primary data line to enable communication between devices using these secondary lines, synchronized with a clock signal, and allocating multiple communication channels in time slots on both primary and secondary data lines to improve data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single data line and clock line are used in SLIMbus communication, then device compatibility and simplicity are maintained, but communication bandwidth and throughput are insufficient for modern audio and video applications
Solution Approach 1:
The patent segments the communication channels by introducing multiple secondary data lines (SD0, SD1, etc.) that can be independently configured and activated. Each secondary data line can operate autonomously to carry additional data traffic, effectively dividing the communication burden across multiple parallel channels while maintaining the original primary data line for backward compatibility.
Solution Approach 2:
The patent adds temporal dimension to the communication protocol by implementing time-division multiplexing where configuration messages are sent during specific time slots to establish secondary data line connections. This allows the system to dynamically allocate bandwidth across multiple dimensions (spatial through multiple lines and temporal through time slots) without requiring all lines to be active simultaneously.
2Productivity
If additional secondary data lines are configured to increase bandwidth, then communication throughput improves, but system configuration and protocol complexity increase
Solution Approach 1:
The patent creates a universal configuration message format that can handle both single-line and multi-line configurations through a unified protocol structure. The same primary data line and clock line infrastructure serves multiple functions: initial device discovery, capability exchange, configuration message delivery, and ongoing data transmission. This multi-functionality reduces the need for separate dedicated control channels.
Solution Approach 2:
The patent implements preliminary configuration actions where capability exchange messages are sent before actual data transfer begins. Devices预先 negotiate their capabilities, number of supported secondary lines, and communication parameters through configuration messages. This preliminary setup phase allows the system to establish optimal communication paths before high-speed data transfer commences, reducing runtime complexity.
3Productivity
If time slot allocation is implemented on multiple data lines, then channel utilization and bandwidth efficiency improve, but timing synchronization requirements increase
Solution Approach 1:
The patent implements periodic time-division multiplexing where each secondary data line is activated in regular time slots according to a predetermined schedule. Configuration messages and data transfers occur in periodic cycles, with each device knowing in advance when it should transmit or receive on each line. This periodic structure simplifies synchronization compared to arbitrary timing, as devices can use simple counters and timers to track their turn.
Solution Approach 2:
The patent incorporates feedback mechanisms through acknowledgment messages sent after configuration and data transfers. Devices confirm successful reception and proper synchronization status, allowing the system to detect and correct timing drift. The feedback loop ensures that even if slight timing variations occur, the system can maintain synchronization by adjusting based on received acknowledgments.
Data Source
AI summary
A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.