Sloped Gate Profile Void Prevention in Semiconductor Devices
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Solution Overview
Problem
The formation of gate electrodes in semiconductor devices often results in voids due to the perpendicular sidewalls of the gate openings, which can affect the integrity and performance of the transistors.
Innovation Solution
A gate-last approach is employed, where a dummy gate electrode with spacers is formed, and after removing the dummy gate, a funnel-shaped opening is created to accommodate the gate electrode, reducing void formation by using etch processes that differentiate the etch rates of the dummy gate stack and spacers, allowing for an open-profile gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If perpendicular sidewalls are used in gate openings, then the gate structure is simple to form, but voids are formed during gate electrode deposition
Solution Approach 1:
The patent applies curvature by transitioning from perpendicular sidewalls to sloped sidewalls in the gate opening. The etch process is specifically designed to create sloped sidewalls that angle inward from the top to the bottom of the opening, eliminating the perpendicular geometry that causes void formation during electrode deposition.
Solution Approach 2:
The patent changes the geometric parameters of the gate opening by controlling the etch rate differential between the dummy gate stack and spacers. By adjusting etch conditions and selecting appropriate etchants, the sidewall angle is optimized to prevent voids while maintaining manufacturing feasibility.
2Ease of manufacture
If dummy gate stack and spacers are etched at the same rate, then the etch process is simple, but the funnel-shaped opening cannot be formed
Solution Approach 1:
The patent applies local quality by creating different etch rates in different regions of the gate structure. The etch process is selectively optimized to etch the dummy gate stack material faster than the spacer material, creating the desired funnel shape with sloped sidewalls where needed while maintaining spacer integrity.
Solution Approach 2:
The patent changes the etch process parameters by selecting etchants with different etch rates for the dummy gate stack and spacer materials. This differential etching is controlled through chemistry selection and process conditions to achieve the precise shape control needed for void-free electrode formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces or prevents voids during gate electrode formation, enhancing the reliability and performance of semiconductor devices by ensuring a more uniform and void-free gate structure.
Implementation Method 1
etch processes that differentiate the etch rates of the dummy gate stack and spacers
Data Source
AI summary
A semiconductor device having an open profile gate electrode, and a method of manufacture, are provided. A funnel-shaped opening is formed in a dielectric layer and a gate electrode is formed in the funnel-shaped opening, thereby providing a gate electrode having an open profile. In some embodiments, first and second gate spacers are formed alongside a dummy gate electrode. The dummy gate electrode is removed and upper portions of the first and second gate spacers are removed. The first and second gate spacers may be formed of different materials having different etch rates.