Small LED Chiplets for Heat Management and Efficiency

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Solution Overview

Problem

Current light-emitting diodes (LEDs) face inefficiencies due to their large size, leading to heat management issues and increased costs, which can be mitigated by developing small-sized LED chiplets that can be fabricated for high-performance operation and integrated into flexible substrates for various applications.

Innovation Solution

The design and fabrication of small-sized LED chiplets involve a heterostructure with specific layers such as n+ GaN, quantum wells, electron blocking layers, and metal contacts, which are printed onto flexible substrates to create high-efficiency lighting devices, including monochromatic and full-color displays, allowing for improved heat management and reduced costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If large-sized LEDs are used, then light output is sufficient, but heat management becomes difficult and costs increase

Engineering Contradiction:
Improveheat managementVSAvoidlight output efficiency
Core Design Contradiction:
TemperatureVSProductivity

Solution Approach 1:

The patent divides a large LED into multiple small-sized LED chiplets (e.g., 20-100 micrometers in size) that can be distributed over a larger area. Each chiplet operates independently with lower power consumption and heat generation, enabling effective heat management while maintaining sufficient total light output through the combined emission of multiple chiplets.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single large LED operating in one dimension to multiple small chiplets distributed across a two-dimensional area. This spatial distribution allows heat to dissipate more effectively across a larger surface area while maintaining the required light output through the cumulative effect of multiple sources.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Temperature

If small-sized LED chiplets are used, then heat management is improved, but fabrication precision requirements increase

Engineering Contradiction:
Improveheat managementVSAvoidchiplet size control
Core Design Contradiction:
TemperatureVSManufacturing precision

Solution Approach 1:

The patent employs selective area growth techniques during MOCVD fabrication to create precisely defined active regions within each chiplet. By controlling the local composition and structure of semiconductor layers in specific areas, the process achieves the required manufacturing precision for small chiplet dimensions while maintaining consistent quality across multiple chiplets.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent performs preliminary patterning and definition of active regions before final chiplet separation. This preliminary action establishes precise boundaries and structures that guide subsequent fabrication steps, ensuring that each small chiplet maintains the required dimensional accuracy and structural integrity after separation from the substrate.

Inventive Principle:
Principle #10Preliminary action

3Temperature

If small-sized LED chiplets are distributed over larger area, then heat management is improved, but device complexity increases

Engineering Contradiction:
Improveheat managementVSAvoidstructure complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent designs each small LED chiplet as a complete, functional unit that can operate independently. This universal design allows individual chiplets to be distributed across a larger area for improved heat management, while each chiplet maintains all necessary functional elements (electrodes, active regions, contact structures) to operate autonomously without requiring complex inter-chiplet interconnections.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent creates multiple identical copies of the same chiplet structure from a single substrate. This copying approach simplifies the overall device architecture by using repeated, standardized units rather than designing complex unique structures for each position. The uniformity of copied chiplets reduces fabrication complexity and facilitates systematic heat dissipation across the distributed array.

Inventive Principle:
Principle #26Copying

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The small-sized LED chiplets enhance light extraction, reduce contact resistance, and increase efficiency, enabling homogeneous carrier injection and high-performance operation while simplifying device design and reducing costs through flexible substrate integration.

Implementation Method 1

One of the layers is called the active region which includes several quantum wells. In designing the LED, one objective is to confine the electrons and holes in the active region in order to force their recombination to emit a photon in the active region.

Methodology Applied
Scientific EffectQuantum confinement:

Implementation Method 2

confine the electrons and holes in the active region in order to force their recombination to emit a photon in the active region

Methodology Applied
Scientific EffectElectroluminescence: Electroluminescence

Data Source

PatentUS9859468B2Small-sized light-emitting diode chiplets and method of fabrication thereof
Publication Date: 2018.01.02 GENESEE VALLEY INNOVATIONS LLC
  • US9859468B2 patent drawing
  • US9859468B2 patent drawing
  • US9859468B2 patent drawing

AI summary

Diode includes first metal layer, coupled to p-type III-N layer and to first terminal, has a substantially equal lateral size to the p-type III-N layer. Central portion of light emitting region on first side and first metal layer includes first via that is etched through p-type portion, light emitting region and first part of n-type III-N portion. Second side of central portion of light emitting region that is opposite to first side includes second via connected to first via. Second via is etched through second part of n-type portion. First via includes second metal layer coupled to intersection between first and second vias. Electrically-insulating layer is coupled to first metal layer, first via, and second metal layer. First terminals are exposed from electrically-insulating layer. Third metal layer including second terminal is coupled to n-type portion on second side of light emitting region and to second metal layer through second via.