SME Instruction Issue Through Two-Phase ZA Tracking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of scheduling Scalable Matrix Extension (SME) instructions in processor devices is exacerbated by the difficulty in detecting and resolving Read-After-Write (RAW) hazards on ZA registers, which are larger and more numerous than conventional registers, leading to inefficiencies in issuing instructions in-order while maintaining high throughput.
Innovation Solution
A two-phase resolution method is employed, where a reservation station performs reduced-precision ZA tracking during the first phase to identify micro-ops with no RAW hazards based on Z and P registers, followed by full-precision tracking in the second phase to confirm the absence of hazards, allowing out-of-order issue of micro-ops with no RAW hazards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If SME instructions are scheduled in-order to maintain simplicity, then device complexity is reduced, but productivity decreases due to difficulty in detecting RAW hazards on ZA registers
Solution Approach 1:
The RAW hazard detection process is segmented into two distinct phases: a first phase that performs reduced-precision tracking to quickly identify potential hazards, and a second phase that performs full-precision tracking to confirm hazards. This segmentation allows the system to maintain in-order scheduling simplicity while improving throughput by efficiently filtering and resolving hazards without requiring complete analysis at every stage.
Solution Approach 2:
The first phase of RAW hazard detection performs preliminary tracking using reduced precision before the second phase performs full-precision tracking. This preliminary action eliminates obvious hazards early in the process, reducing the workload for subsequent hazard detection and allowing more instructions to be issued per cycle while maintaining correctness.
2Measurement precision
If full-precision ZA tracking is performed for every micro-op, then measurement precision of RAW hazards is improved, but loss of time increases due to processing overhead
Solution Approach 1:
The hazard detection process is divided into two phases with different precision levels. The first phase uses reduced-precision tracking to quickly screen micro-ops and identify obvious hazards, while the second phase applies full-precision tracking only to micro-ops that require further verification. This segmentation reduces the total time spent on hazard detection while maintaining accurate identification of all RAW hazards.
Solution Approach 2:
Instead of applying full-precision tracking to all micro-ops, the system applies reduced-precision tracking as a partial action to filter out obvious cases first. Full-precision tracking is then applied only where necessary, reducing overall processing time while ensuring that no hazards are missed. This selective application of precision levels optimizes the balance between accuracy and speed.
Data Source
AI summary
Enabling high-performance Scalable Matrix Extension (SME) instruction issue in processor devices is disclosed herein. In some aspects, a processor device comprises a reservation station circuit configured to perform, during a first phase, a reduced-precision vector accumulator (ZA) tracking operation on micro-ops for which corresponding vector (Z) registers and corresponding predicate (P) registers are ready. Based on the reduced-precision ZA tracking operation, the reservation station circuit selects a first micro-op and a second micro-op having no Read-After-Write (RAW) hazard with respect to the ZA registers. During a subsequent second phase, the reservation station circuit performs a full-precision ZA tracking operation on the first micro-op and the second micro-op, and selects one as a micro-op for issue for which the full-precision ZA tracking operation indicates no RAW hazard exists with respect to the ZA registers. The reservation station circuit then issues the selected micro-op for execution.