SMPS Comparator Timing for Stable Pulse-Skipping Transitions
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Solution Overview
Problem
Switched-mode power supplies experience oscillations and inefficiencies during transitions between pulse skipping and continuous conduction modes, particularly when dealing with medium output loads, and there is a need for improved energy efficiency and reduced energy consumption.
Innovation Solution
Implementing a modified comparator that adjusts its output signal during a portion of the conduction phase to determine load size and transition between modes, ensuring accurate mode switching by comparing output voltage with a reference voltage and using a zero-current detection circuit to manage transitions without delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the power supply uses conventional mode switching between pulse skipping and continuous conduction modes, then it can handle varying load conditions, but oscillations occur on the output voltage during transitions
Solution Approach 1:
The patent applies preliminary action by forcing the comparator output to a specific state (one) for a predetermined duration (at least 20% of the switch conduction time) before the actual mode transition occurs. This preliminary forcing of the comparator output prepares the control system in advance, ensuring that the transition from pulse skipping mode to continuous conduction mode happens smoothly without causing output voltage oscillations. The predetermined timing ensures the transition occurs at the optimal moment in the switching cycle.
2Speed
If the comparator responds immediately to voltage changes during mode transition, then it provides fast response, but causes oscillations and inefficiencies
Solution Approach 1:
The invention implements preliminary action by pre-setting the comparator output state before the actual mode transition. By forcing the comparator output to one for at least 20% of the conduction time, the system prepares the control logic in advance, allowing a smooth transition that avoids energy-wasting oscillations while maintaining fast overall response. This eliminates the need for immediate comparator response that would cause instability.
Solution Approach 2:
The patent employs periodic action by synchronizing the comparator output forcing with the switching cycle. The comparator output is forced during specific portions of the conduction phase (at least 20% of the conduction time), creating a periodic control pattern that aligns with the switching frequency. This periodic forcing ensures consistent, oscillation-free transitions while maintaining energy efficiency across all operating cycles.
3Productivity
If the power supply transitions between modes without delayed comparator response, then it achieves quick mode switching, but experiences oscillations particularly with medium output loads
Solution Approach 1:
The patent applies preliminary action by forcing the comparator output to one for at least 20% of the conduction time before the mode transition completes. This preliminary action prepares the control system in advance, enabling quick mode switching without the oscillations that would otherwise occur with medium output loads. The timing is carefully coordinated with the switching cycle to ensure smooth transitions.
Data Source
AI summary
A switched-mode power supply includes a first switch coupling a first node receiving a power supply voltage to a second node supplying an output voltage and a second switch coupling a third node receiving a reference voltage to the second node. A comparator functions to compare the output voltage with a comparison voltage. When the switched-mode power supply is operating in a pulse skipping mode, the comparator generates an output signal indicating that the output voltage is higher than the comparison voltage during part of the conduction phase of the first switch. The switched-mode power supply transitions from a pulse skipping mode to the continuous conduction mode as soon as the output voltage is lower than the comparison voltage.


