Pipelined SNN Memory Architecture for Parallel Spike Processing
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Solution Overview
Problem
Scalability and efficient processing of spiking neural networks (SNNs) are challenging due to the significant computational demands of simulating large biological neural networks (BNNs) with billions of neurons and synapses, requiring advanced memory architectures that can handle synaptic connections and learning processes efficiently.
Innovation Solution
A pipelined memory architecture using special-purpose memory devices as nodes, each representing a group of neurons, with separate memory sections for processing inbound spikes, identifying synaptic connections, and performing synaptic current and membrane potential calculations in parallel, while managing synaptic connection strengths and delays through a pipeline architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a traditional memory architecture is used to process spikes in SNNs, then the system can handle basic neural network operations, but the processing speed and efficiency are insufficient due to sequential access patterns and lack of parallelization
Solution Approach 1:
The memory architecture is segmented into multiple banks (e.g., bank 0, bank 1, bank 2, bank 3) that can be accessed in parallel. Each bank handles specific synaptic connections, allowing simultaneous processing of multiple spikes without sequential access delays. This segmentation enables the system to achieve high processing throughput by dividing the memory space into independent, concurrently accessible units.
Solution Approach 2:
The patent introduces a bank dimension to the traditional memory architecture, transforming a single-dimensional sequential access structure into a multi-dimensional parallel structure. By organizing memory into banks that can be accessed simultaneously along the bank dimension, the system achieves parallel processing capability while maintaining efficient access patterns within each bank.
2Quantity of substance
If computing resources are increased to handle more neurons and synapses, then the SNN can model larger biological neural networks, but the device complexity and resource requirements increase significantly
Solution Approach 1:
The patent merges memory storage and synaptic computation functions into a unified memory architecture. Synaptic weights, neuron parameters, and spike data are integrated within the same memory banks, eliminating the need for separate computing units and reducing overall system complexity. This merging allows the system to scale to large numbers of neurons and synapses without proportionally increasing device complexity.
Solution Approach 2:
The memory banks are designed to perform multiple functions: storing synaptic weights, holding neuron parameters, buffering spike data, and performing computational operations. This multi-functionality reduces the need for specialized hardware components, allowing the system to handle large-scale neural networks with limited computing resources by efficiently utilizing the same hardware for multiple purposes.
3Speed
If memory access is optimized for speed, then spike processing becomes faster, but the ability to manage complex synaptic connections and maintain accurate timing information deteriorates
Solution Approach 1:
The memory architecture pre-organizes synaptic connection data and spike routing information before processing occurs. Synaptic weights and connection patterns are pre-loaded into appropriate memory banks, and spike routing tables are pre-computed, enabling fast access during actual processing without compromising the accuracy of synaptic connections or timing information.
Solution Approach 2:
The patent introduces control logic and addressing mechanisms as intermediaries between the fast memory access paths and the synaptic computation operations. These intermediaries ensure that high-speed access to memory banks does not compromise the accuracy of synaptic connections by properly managing data retrieval, validation, and delivery to computation units.
Data Source
AI summary
The present disclosure is directed to pipelining operations of a spiking neural network (SNN) that performs in-memory operations. To model a computer-implemented SNN after a biological neural network, the architecture in the present disclosure involves different memory sections for storing inbound spike messages, synaptic connection data, and synaptic connection parameters (e.g., states). The section of memory containing synaptic connection data to identify matching inbound spike messages. In parallel, the section of memory containing synaptic connection parameters may be accessed to perform various neuromorphic calculations, synaptic plasticity and outbound spike message generation.