SoC Block Isolation for Targeted Verification
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Solution Overview
Problem
The increasing integration of semiconductor devices in electronic apparatuses has led to a rise in the time required for verifying semiconductor chips, as existing test methods are inefficient in isolating and testing individual blocks within a system on chip.
Innovation Solution
A test method and system that involves booting up a system on chip, storing input values for each block, disabling all blocks except the test block, initializing the test block with a specific input value, and using a verifier to perform verification based on the block's operation results, thereby reducing the complexity and duration of the testing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all blocks in the system on chip are tested simultaneously using existing test methods, then comprehensive verification is achieved, but the test time increases significantly
Solution Approach 1:
The system on chip is divided into multiple independent testable blocks. The test method segments the verification process by isolating each block individually through disabling other blocks, allowing targeted testing of specific blocks rather than testing the entire system simultaneously. This segmentation enables parallel test planning and reduces overall test time while maintaining verification completeness.
Solution Approach 2:
Input values are captured and stored during the boot-up phase before formal testing begins. This preliminary action allows the test block to be pre-initialized with realistic input data that was actually used during system startup, enabling more efficient and accurate subsequent verification without requiring full system operation.
2Reliability
If the entire system on chip is tested as a whole, then system-level interactions are verified, but the complexity of the testing process increases
Solution Approach 1:
The testing process is segmented into block-level tests that can be independently configured and executed. By disabling components of blocks other than the test block, the method simplifies the testing complexity while maintaining the ability to verify system-level interactions through coordinated block testing. Each block can be tested in isolation with reduced complexity.
Solution Approach 2:
Instead of testing all blocks simultaneously with full system complexity, the method applies partial action by focusing tests on one block at a time while disabling others. This reduces the immediate testing complexity to manageable levels while still achieving comprehensive system verification through multiple targeted test passes.
3Ease of operation
If all blocks remain enabled during testing, then system operations are maintained, but the precision of block-level measurement decreases
Solution Approach 1:
The system operates in segmented modes: during normal operation all blocks remain enabled, but during testing specific blocks are isolated by disabling others. This segmentation allows precise block-level measurements when needed while maintaining system operation continuity during non-test periods. The boot-up phase captures input values that preserve operational context for accurate block-level testing.
Data Source
AI summary
A test method for a system on chip, the test method including: receiving a system on chip including a plurality of blocks; booting up the system on chip; storing input values that are input to each of the plurality of blocks, while booting up the system on chip; and performing a test on a first block among the plurality of blocks, wherein performing the test on the first block includes: disabling components of each of the plurality of blocks except the first block, and inputting a first input value to the first block to initialize the first block, wherein the first input value is one of the stored input values that was input to the first block while booting-up the system on chip.