Core-to-Core Mismatch Reduction in Multi-Core SOC Manufacturing
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Solution Overview
Problem
In System-On-Chip (SOC) applications, the scaling-down process increases process-induced and environment-induced inconsistencies in critical dimensions between designed and manufactured components, leading to core-to-core mismatches in multi-core SOC products, which result in performance issues and reduced design margins in portable electronic devices.
Innovation Solution
A method involving the measurement of representative patterns on each core to calculate mismatch values, with a processor determining tuning amounts to adjust manufacturing conditions, such as lithography energies, etching processes, and mask settings, to reduce core-to-core mismatches by modulating the gate lengths and electronic characteristics of subsequent SOC products.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the scaling-down process is implemented to increase functional density, then production efficiency increases and costs decrease, but process-induced and environment-induced inconsistencies in critical dimensions increase, leading to core-to-core mismatches
Solution Approach 1:
The patent applies preliminary action by measuring and characterizing process variations and environmental influences on critical dimensions before final product manufacturing. Representative patterns are measured in advance to establish tuning amounts that compensate for expected variations, allowing proactive correction rather than reactive adjustment.
Solution Approach 2:
The patent utilizes parameter changes by adjusting lithography energies, etching process parameters, and mask settings based on measured representative pattern data. These parameter modifications are specifically tailored to compensate for identified process-induced and environment-induced variations, thereby maintaining critical dimension consistency despite scaling challenges.
2Manufacturing precision
If representative patterns are measured and tuning amounts are calculated for each core, then core-to-core mismatches are reduced, but measurement and processing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the SOC product into multiple cores, each with its own representative pattern that is measured and characterized independently. This allows specific tuning amounts to be calculated for each core based on its unique process variations and environmental conditions, enabling precise individual correction without requiring complex system-wide adjustments.
Solution Approach 2:
The patent uses copying by creating representative patterns that replicate the critical dimensional characteristics of actual core structures. These representative patterns serve as simplified copies that can be measured more easily while still providing accurate data for determining tuning amounts, thereby reducing measurement complexity while maintaining precision.
Data Source
AI summary
Methods for reducing core-to-core mismatch are provided. The method includes measuring gate lengths of a representative pattern of each core in a first lot of SOC products by a measurement apparatus. Each of the SOC products in the first lot includes more than two cores identical to each other. The method also includes determining a tuning amount according to the differences between the gate lengths of each core, and adjusting at least one mask for critical dimensions of gate length of each core in a second lot of SOC products respectively according to the tuning amounts.