SoC FPGA Shared-Memory Architecture for Edge AI Acceleration
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Solution Overview
Problem
Existing AI computing systems face challenges in achieving efficient, low-cost, and high-performance edge artificial intelligence computing, with pure MCU solutions offering low computational performance and fully customized hardware being costly and difficult to design.
Innovation Solution
A system architecture based on SoC FPGA that includes an MCU subsystem and an FPGA subsystem with a shared memory interface, enabling the use of a customizable accelerator to accelerate AI algorithms, reducing power consumption and area while ensuring high computing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pure MCU is used to provide fixed hardware structure, then area and power consumption are reduced, but computational performance is low
Solution Approach 1:
The system divides computational tasks into two segments: general-purpose tasks handled by the MCU and AI-specific acceleration tasks handled by the FPGA accelerator. This segmentation allows the MCU to remain low-power while the FPGA handles only the computationally intensive AI workloads, resolving the contradiction between computational performance and power consumption.
Solution Approach 2:
The system dynamically allocates computational work between the MCU and FPGA accelerator based on task requirements. The compilation toolchain automatically identifies AI algorithms that benefit from acceleration and generates appropriate instruction calls, enabling the system to adapt its computational architecture dynamically rather than being statically fixed.
2Productivity
If fully customized hardware is used, then computing performance requirements are met, but design cost and complexity are high
Solution Approach 1:
The FPGA accelerator is designed as a universal computing resource that can execute multiple different AI algorithms through reconfiguration. Rather than designing separate custom hardware for each algorithm, the system uses a single multi-functional FPGA accelerator that can be programmed to handle various AI workloads, significantly reducing design cost and complexity while maintaining high computational performance.
Solution Approach 2:
The system changes the operational parameters of the FPGA accelerator through software compilation and configuration rather than hardware redesign. The compilation toolchain generates bitstreams that reconfigure the FPGA's logic elements and resources to match the specific AI algorithm being executed, allowing performance optimization without increasing design complexity.
3Ease of operation
If high-level synthesis platform based on FPGA is used, then algorithm implementation is easy, but area and power requirements are not met
Solution Approach 1:
The system applies local quality optimization by implementing only the specific AI algorithms that require acceleration in the FPGA, while leaving other functionality to the MCU. The compilation toolchain analyzes the AI model and generates acceleration instructions only for the computationally intensive portions, allowing easy algorithm implementation while minimizing the area and power consumed by the FPGA accelerator.
4Speed
If data is processed through traditional interfaces, then system compatibility is maintained, but data access speed is slow
Solution Approach 1:
The patent introduces a shared memory interface as an intermediary between the MCU and FPGA accelerator. This shared memory serves as a high-speed data exchange buffer that eliminates the need for complex traditional interfaces while maintaining system compatibility. The shared memory allows the accelerator to read input data and write output results directly at high speeds without going through multiple interface conversion stages.
Data Source
AI summary
A system architecture based on SoC FPGA for edge artificial intelligence computing includes an MCU subsystem and an FPGA subsystem. The FPGA subsystem includes: an accelerator for accelerating artificial intelligence algorithm; and a shared memory used as an interface between the accelerator and the MCU subsystem. The shared memory is configured to upload the data to be calculated and to retrieve the operation result; the accelerator is configured to read the data from the shared memory independently and to write back the operation result. The system architecture has the advantages of small hardware area, low power consumption, high computing performance and easy use, and the design process is simple and flexible.