Multi-core SoC Dynamic Power Management via Task Rate Sampling

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Solution Overview

Problem

Efficient power management in mobile devices with multi-core processors is challenging due to demanding processing tasks, leading to battery life issues without increasing device size or weight.

Innovation Solution

A control method for a system-on-chip with a multi-core processor that detects runnable tasks and voltage/clock rates to perform hotplug operations, optimizing core activation based on task rates and power conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple cores are activated to handle demanding processing tasks, then processing performance is improved, but power consumption increases

Engineering Contradiction:
Improveprocessing performanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The system dynamically adjusts the number of active cores based on real-time workload conditions. The kernel continuously monitors runnable task rates and driving voltage/clock levels, activating or deactivating cores as needed to match actual processing demands, thereby optimizing the balance between performance and power consumption

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters (core activation state) based on detected conditions. When the runnable task rate and voltage/clock levels indicate high workload, more cores are activated; when conditions indicate low workload, cores are deactivated to reduce power consumption

Inventive Principle:
Principle #35Parameter changes

2Loss of energy

If cores are deactivated to save power, then power efficiency is improved, but processing capability deteriorates

Engineering Contradiction:
Improvepower efficiencyVSAvoidprocessing capability
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The system implements a feedback mechanism where the kernel continuously monitors system state (runnable task rate, voltage, clock speed) and uses this information to make informed decisions about core activation. This feedback loop ensures that cores are deactivated only when workload conditions genuinely support power-saving mode, preventing degradation of processing capability

Inventive Principle:
Principle #23Feedback

3Loss of energy

If hotplug operations are performed frequently to optimize power usage, then power efficiency is improved, but system stability deteriorates

Engineering Contradiction:
Improvepower efficiencyVSAvoidsystem stability
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The system performs preliminary sampling of runnable task rate and voltage/clock levels before executing hotplug operations. By checking whether these parameters satisfy hotplug conditions through multiple samples, the system prepares and validates the necessity of core activation/deactivation before actually performing the operation, reducing unnecessary transitions

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The kernel performs periodic sampling of system parameters at predetermined time intervals rather than continuously monitoring and reacting. This periodic approach smooths out transient fluctuations and prevents overly frequent hotplug operations, thereby maintaining system stability while still achieving power optimization

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS9746902B2System-on-chip including multi-core processor and dynamic power management method thereof
Publication Date: 2017.08.29 SAMSUNG ELECTRONICS CO LTD
  • US9746902B2 patent drawing
  • US9746902B2 patent drawing
  • US9746902B2 patent drawing

AI summary

Provided is a control method of a system-on-chip including a multi-core processor. The control method includes detecting a rate of runnable tasks to be performed in the multi-core processor and a driving voltage or a driving clock of the multi-core processor, determining whether variation of the rate of the runnable tasks sampled from a first time point to a current time and variation of the driving voltage or the driving clock sampled from a second time point to the current time satisfy a hotplug condition, andhotplugging in or out at least one core included in the multi-core processor when the rate of the runnable tasks and the driving voltage or the driving clock each satisfy the hotplug condition.