SoC Isolation Wrapper Latch for Low-Power Standby Routing

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Solution Overview

Problem

Existing SoC designs face challenges in efficiently routing isolation signals between AON domains, especially when these domains are far apart, due to the need for additional buffering which increases area and is susceptible to noise.

Innovation Solution

The implementation of a voltage level detector powered by either a switchable or AON power supply to generate isolation signals, combined with an ISO latch that latches the signal before power is lost, allowing clean isolation signals to reach switchable domains and AON domains without additional buffering.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If buffers are placed in AON domain islands along the path of isolation signals, then signal routing is enabled, but area increases

Engineering Contradiction:
Improvesignal routing capabilityVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent introduces a special buffer cell type that operates in both AON and switchable power domains as an intermediary solution. This buffer can be powered by either AON or switchable power supply, allowing it to function as a mediator that bridges the gap between AON domains and switchable domains, enabling isolation signal routing without requiring extensive AON domain infrastructure or top metal routing resources.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The buffer cell is designed with multi-functionality to operate in dual power domain modes. It can be configured to run on AON power supply when located in AON domains or on switchable power supply when located in switchable domains, making it a universal solution that eliminates the need for separate buffer implementations for different routing scenarios.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If AON buffers are designed as standard cells receiving both AON and switchable power supply, then signal routing is enabled, but area increases due to parallel power grids

Engineering Contradiction:
Improvesignal routing capabilityVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The buffer cell implements dynamic power supply selection based on its operational context. The buffer can dynamically switch between AON and switchable power supply modes depending on whether it is located in an AON domain or a switchable domain, allowing the same cell design to adapt to different power domain environments without requiring parallel power grid infrastructure.

Inventive Principle:
Principle #15Dynamics

3Length of stationary object

If super buffers are used to route signals over the middle of the SoC, then long distance routing is enabled, but area increases and noise susceptibility increases

Engineering Contradiction:
Improvesignal routing distanceVSAvoidchip area
Core Design Contradiction:
Length of stationary objectVSArea of stationary object

Solution Approach 1:

The patent segments the isolation signal routing path into multiple manageable segments, placing buffer cells at strategic locations along the routing path. Instead of using a single large super buffer, the signal is buffered in stages through multiple smaller buffer cells distributed across the chip, which reduces the burden on any single buffer and allows for better signal integrity management over long distances.

Inventive Principle:
Principle #1Segmentation

4Reliability

If buffers are used to route isolation signals through switchable domains, then signal transmission is enabled, but power consumption increases during standby mode

Engineering Contradiction:
Improvesignal transmission capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The buffer cells are pre-configured with dual power supply capability during design, allowing them to be seamlessly switched between AON and switchable power modes. This preliminary preparation enables the system to transition to zero-power operation during standby mode without requiring complex runtime reconfiguration, as the buffers are already designed to accept switchable power supply.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12306652B2System on a chip (SoC) having a low power mode of operation
Publication Date: 2025.05.20 NXP USA INC
  • US12306652B2 patent drawing
  • US12306652B2 patent drawing
  • US12306652B2 patent drawing

AI summary

In an integrated circuit, a first always on (AON) domain generates an isolation signal to enter standby mode. A switchable power domain propagates the isolation signal. A voltage level detector outputs an indicator which indicates whether a voltage of the switchable power supply is above or below a voltage threshold. An isolation wrapper circuit includes a pass-through latch selectively enabled based on the output of the voltage level detector. The pass-through latch receives the propagated isolation signal and provides a value of the propagated isolation signal at its output while enabled, but maintains a latched value at its output, regardless of changes in value of the propagated isolation signal, while disabled. The wrapper circuit also includes an isolation circuit which receives signals from circuitry within the switchable power domain and selectively isolates the received signals from a second AON power domain based on the output of the pass-through latch.