3D SoC-Memory Bonding Layout for Compact High-Bandwidth Packaging
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Solution Overview
Problem
The semiconductor industry faces challenges in further reducing the physical size of semiconductor devices while maintaining high performance and low power consumption, as existing bonding processes for stacked and bonded semiconductor devices are complex and in need of improvement.
Innovation Solution
The integration of a first and second system on chip devices with wide I/O memory devices and integrated fan out technology, utilizing hybrid bonding and through silicon vias to form a high-performance, low-cost structure, involving processes such as hybrid bonding, encapsulation, and redistribution layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If repeated reductions in minimum feature size are used to improve integration density, then more components can be integrated into a given area, but the physical size reduction and performance requirements cannot be fully met
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional stacked integration by bonding multiple semiconductor dies together vertically. This allows continued increase in integration density without further reducing the minimum feature size on each die, thereby avoiding the limitations of continued scaling while meeting physical size reduction requirements.
Solution Approach 2:
The patent implements a stacked configuration where multiple semiconductor dies are bonded together in a vertical arrangement, with each die containing active circuits. This nested structure allows multiple functional layers to be integrated within a compact footprint, achieving high integration density without proportionally increasing the device's physical dimensions.
2Length of moving object
If stacked and bonded semiconductor devices are used to reduce physical size, then miniaturization is achieved, but the bonding processes become complex and require sophisticated techniques
Solution Approach 1:
The patent performs preliminary actions during die fabrication by forming bump electrodes and bonding pads on the dies before the bonding step. This pre-preparation simplifies the subsequent bonding process by ensuring all necessary structures are already in place, reducing the complexity of the bonding operation itself while achieving the desired miniaturization.
Solution Approach 2:
The patent employs self-aligning features such as bump electrodes that automatically position dies relative to each other during bonding. This self-service mechanism reduces the precision requirements for external alignment tools and procedures, simplifying the bonding process while maintaining the compact stacked structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of compact semiconductor devices with enhanced electrical connectivity and reliability, achieving high bandwidth and reduced latency through efficient integration of active circuits on separate substrates.
Implementation Method 1
utilizing hybrid bonding and through silicon vias to form a high-performance, low-cost structure
Implementation Method 2
encapsulating the first system on chip device and the second system on chip with a first encapsulant
Data Source
AI summary
A semiconductor device and method of manufacture are provided wherein the semiconductor device includes a first system on chip device bonded to a first memory device, a second system on chip device bonded to the first memory device, a first encapsulant surrounding the first system on chip device and the second system on chip device, a second encapsulant surrounding the first system on chip device, the second system on chip device, and the first memory device, and a through via extending from a first side of the second encapsulant to a second side of the first encapsulant, the through via being located outside of the first encapsulant.