SoC Pin Fault Detection Using Power-Ready Signal Monitoring
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Solution Overview
Problem
Current integrated circuit technologies lack effective fault detection mechanisms for chip pins, leading to indeterminate behavior and potential failures due to malfunctions in receiving reset signals, which can result in immediate or future chip failures.
Innovation Solution
Implementing a fault detection circuit that monitors characteristics of chip pads to generate fault indicators by observing the logic states of power ready signals and voltage levels, using power detectors and flip-flops to identify faults such as stuck signals or unstable transitions, and storing these indicators for processing by a fault controller circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fault detection circuitry is added to monitor chip pins, then reliability of chip operation is improved, but device complexity increases
Solution Approach 1:
The patent implements preliminary monitoring of reset signals at chip pins before they can cause failures. The fault detection circuit continuously observes reset signal characteristics and generates early warnings of potential pin malfunctions, allowing preventive action before actual chip failures occur.
Solution Approach 2:
The patent introduces an intermediary fault detection circuit between the external reset signal source and the chip's internal reset logic. This intermediary monitors the reset signal for anomalies (such as unexpected transitions or voltage level issues) and can prevent faulty signals from reaching critical chip components, thereby improving reliability without requiring changes to the core chip architecture.
2Measurement precision
If monitoring of power ready signals is implemented, then fault detection precision is improved, but manufacturing complexity increases
Solution Approach 1:
The fault detection circuit utilizes the existing power ready signals that are already present in the chip architecture for its monitoring function. By self-serviceing from existing signal infrastructure rather than requiring entirely new sensing mechanisms, the patent achieves precise fault detection while minimizing additional manufacturing complexity.
Solution Approach 2:
The monitoring circuit is designed to handle multiple types of faults using the same power ready signal infrastructure. A single fault detection mechanism can identify various pin malfunctions including stuck-at faults, transition faults, and voltage level faults, thereby achieving high detection precision without proportionally increasing manufacturing complexity through multiple specialized circuits.
Data Source
AI summary
A first power supply pad is configured to provide a first power supply to a power domain of the SoC in which the first power supply pad is configured to receive the first power supply from a source external to the SoC. A first signal pad is configured to receive a power ready signal from external the SoC which indicates when the first power supply to the power domain is fully powered up. A first power detector is configured to provide a first power detected output, which, when asserted, indicates presence of a power supply voltage on the first power supply pad. A fault detection circuit coupled to the first power detector and the first signal pad is configured to generate a set of fault flags in response to monitoring a relationship between the first power detected output and a logic state of the power ready signal.